Motorola Corporation

William L Martino, Jr

Scott Ives Remington

Jerry D Moench

Dimitris C Pantelakis

Ruey J Yu

Wai Tong Lau

Frank Arlen Miller

Kichio Abe

Eric S Powers

Derrick Leach

An integrated circuit device includes low voltage internal circuitry and a first external pin which receives a first information signal. The first information signal provides operating information within a predetermined voltage range. The device includes a mode detector coupled to the first external pin. The mode detector provides a mode enable signal in response to the first information signal being at a voltage that is outside the predetermined voltage range. The device further includes a switchable regulator which provides a supply voltage to the low voltage internal circuitry to power the low voltage internal circuitry at a regulated voltage in a normal mode of the integrated circuit memory and at a higher voltage than the regulated voltage in response to the mode enable signal.

Circuit and method for enabling semiconductor device burn-in

A memory (10) such as a current sensing static random access memory (SRAM) achieves fast write recovery through bit line loads and two additional mechanisms. First, an additional load (252) on shared data lines also becomes active to speed the write recovery process. Second, multiple columns (200, 202, 204) are connected to common data lines during write recovery so that a column written to during a write cycle may be again precharged in part by charge sharing using the charge stored in other columns. These two mechanisms allow fast write recovery with minimum column pitch and avoid the problems which would be encountered if the loads were placed on the write data line.

Memory device with fast write recovery and related write recovery method

A dynamic random access memory has a bit of data selected by a multiplexed address. The row address latches twice as much data as can be selected by the column address which follows the row address. After the column address has been utilized, there is still a one of two selection between two bits of data required. One of the row addresses provides the final selection between the two bits of data. An array toggle signal available from an extra pin is used to switch the state of the internal signal which corresponds to the one row address signal which makes the final one of two selection. The array toggle signal thus makes it possible to access any of the latched data in a high speed mode in which only the column address is changed to select among the bits of data which are already latched.

Structure and method for improving high speed data rate in a DRAM

A row decoder includes a logic decoder, a word line driver circuit, and first and second coupling circuits. The logic decoder provides a logic high in an inactive cycle and when selected in an active cycle, and a logic low when deselected in the active cycle. Each of a plurality of word line driver circuits receive a decoded address signal which corresponds to that particular driver circuit, each have an output coupled to a corresponding word line, and each have an input which, when at a logic high, causes that word line driver to couple its corresponding decoded address signal to its corresponding word line. The first coupling circuit couples the output of the logic decoder to the input of only the driver circuit which corresponds to an active decoded address signal during the active cycle, and for coupling the output of the logic decoder to all of the driver circuits in the inactive cycle. The second coupling circuit couples the word line which corresponds to the active decoded signal to the output of the logic decoder when the logic decoder is deselected during the active cycle.

Row decoder

An integrated circuit which has serially connected clock drivers for generating sequential clock signals further includes test circuitry for testing for the occurence of the clock signals. The test circuitry includes a current source for each of the sequential clock signals each of which is enabled upon receiving its associated clock signal. Consequently, the current sources are sequentially enabled until a clock signal fails to occur at which time no more clock signals occur so that no more current sources are enabled. The current sources are connected to a probe pad which is accessible external to the integrated circuit. Test apparatus for detecting the enabled current sources can be connected to the integrated circuit at the probe pad.

Clock signal test circuit

A logic decoder provides a true output signal at a first logic state when selected during an active cycle and during an inactive cycle, and at a second logic state when deselected. The logic decoder also provides a complementary output signal. A word line driver circuit couples decoded address signals to respective word lines when the output signal is in the first logic state. A coupling circuit couples one of first and second word lines to ground during the active cycle. A coupling transistor couples the first and second word lines together in response to receiving the complementary output signal at the first logic state.

A substrate bias voltage regulator selectively provides one of two predetermined substrate bias voltage levels in response to a timing signal. The selection of substrate bias voltage level is achieved via a reference generator circuit which provides one of two predetermined reference voltages to a control circuit which regulates the substrate bias voltage to the selected level.

Substrate bias voltage regulator

A balanced differential circuit is provided which is useful as an address buffer in digital memories. The circuit is illustrated as a single ended input circuit having complementary outputs. Capacitors are used to couple imbalancing signals into the circuit. Through selective timing of load devices within the circuit power dissipation is kept to a minimum.

Differential capacitive buffer

A random access memory includes a column of static MOS storage cells. Two sense-write conductors are coupled to each cell in the column. Each sense-write conductor is also coupled, respectively, to a termination MOSFET. The first sense-write conductor of each column of storage cells is coupled by means of a first coupling MOSFET to a first bit-sense conductor. The second sense-write conductor of each column of storage cells is coupled, by a second MOSFET to a second bit-sense conductor. Each pair of sense-write conductors is coupled to a V.sub.DD conductor by a separate charging MOSFET having its gate electrode coupled to a circuit for generating a pulse at the end of a write cycle. Since at the end of any write operation, the two bit-sense conductors and the two sense-write conductors of the selected column will be at opposite voltage levels, the pulse very rapidly precharges the voltages of the two sense-write conductors and of the two bit-sense conductors to levels which ensure that the data stored in the storage cell next selected will not be destroyed as a result of the opposite voltage levels of the two bit-sense conductors acting to write an undesired state into the storage cell selected next. The read access time of the memory is reduced by the amount of time required by the termination MOSFETS to charge a sense-write conductor and a bit-sense conductor to a MOSFET threshold drop below V.sub.DD minus the time required for the charging MOSFETs to precharge the sense-write and bit-sense conductors.

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Austin, TX, United States of America

William L Martino, Jr