International Business Machines Corporation

William L Bucossi

Albert Alexander DeBrita

Bret Roberts Dale

Darin James Daudelin

Hongfei Wu

A design structure and more particularly to a design structure to minimize driver output slew rate variation. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to control the slew rate of the output signal. A delay circuit is coupled to an output of the driver circuit, where the delay circuit has a delay proportional to a desired target slew rate of the driver output signal. A first comparator for detecting when the driver output signal rises through a specified level, and a second comparator for detecting when the driver output falls through a second specified level are included. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases (voltage-time relationships) of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

Structure for time based driver output transition (slew) rate compensation

Apparatus controlling the driver output slew rate that includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

Time based driver output transition (slew) rate compensation

Apparatus and method for controlling the driver output slew rate. The apparatus includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

A digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock signal and a reference voltage, and generates a first output signal. The second differential comparator circuit receives the positive and negative differential clock signal, and generates a second output signal. The third differential comparator circuit receives the reference voltage and the negative differential clock signal, and generates a third output signal. A high-high detecting circuit receives the first output signal, and the third output signal, and generates an Enable signal. The digital clock generation circuit further includes a latch circuit which receives the second output signal, and the Enable signal and generates a digital clock signal. The latch circuit comprises a latch with glitch or noise immunity.

Receiver circuits for generating digital clock signals

A level shift circuit that reduces PMOS to NMOS device contention whole decreasing output rise delays. The invention includes a device, comprising: a level shift circuit for shifting a signal at a first voltage at an input node to a second voltage at an output node; a boost circuit, driven by the second voltage, for decreasing a transition time of the signal between the first and second voltage; and a trigger circuit, coupled to an input of the boost circuit, for turning off the boost circuit when the signal at the output node reaches a predetermined voltage level.

Level shift circuitry having delay boost

A driver including boost circuitry for reducing tri-state delay. Boost circuitry includes boost legs ( ) and ( ) having boost delay chains ( ) and ( ), respectively. Subcircuits ( ) and ( ) may include a series of inverters or other devices to delay a tri-state enable signal (EN ) or (EN BAR) for a predetermined amount of time substantially equivalent to the time it takes for a first signal (A ) to travel from input pin A to PAD. Transient current provides a boost by discharging or charging output nodes (G ) and (G ), respectively. Boost legs ( ) and ( ) remain on for the length of time it takes for enable signal (EN ) or (EN BAR) to travel through subcircuits ( ) and ( ). The boost increases the rate of transition of output nodes (G ) and (G ) thereby reducing the delay of tri-state signal (EN ).

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Burlington, VT, United States of America

William L Bucossi