Intel Corporation

William Knolla

Douglas Raymond Moran

Michael N Derr

Alon Naveh

Ohad Falik

Michael T Klinglesmith

Shaun M Conrad

Reuven Rozic

Jawad Haj-Yihia

Christopher J Lake

Hartej Singh

Bhushan Vaidya

Sm M Rahman

Yitschak Kapschitz

Varghese George

Sanjeev S Jahagirdar

David I Poisner

Mikal Hunsaker

Zohar Bogin

Achmed Rumi Zahir

Darren L Abramson

Neil W Songer

Vasudev Bibikar

Irwin J Vaz

Adit D Tarmaster

In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.

Handling a partition reset in a multi-root system

A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.

Interconnect to communicate information uni-directionally

In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.

System and method for initiating a reduced power mode for one or more functional blocks of a processor based on various types of mode request

Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media are described herein for transitioning a computing device between a first state in which the computing device uses a first amount of power and a second state in which the computing device uses a second, greater amount of power. The computing device may include a shared wake pin to which a first external device and a second external device may be operably coupled, and a communication bus to which the first external device is connected and the second external device is not. Responsive to receipt of a wake signal at the wake pin, the computing device may transition between states, send an instruction to the first external device over the communication bus, and determine whether the first or second external device initiated the wake signal based on a response at the wake pin.

Determination of wake signal initiation on shared wake pins in computing devices

Embodiments of methods and apparatus for entering an activity alignment on state from an activity alignment off state; masking one or more traffic flows that are received during at least a part of the activity alignment on state; and entering the activity alignment off state from the activity alignment on state, after being in the activity alignment on state for at least a first time period, based at least in part on said masking the one or more traffic flows. Additional variants and embodiments are also disclosed.

Activity alignment algorithm by masking traffic flows

Techniques for determining a communication interface of a computer platform. In an embodiment, a power management unit of a computer platform provides to an agent of the platform an indication of a power state. In certain embodiments, the agent determines, based on the indication of the power state, that an interface is expected to be available. The agent may designate information for transmission via the first interface&#x2014;e.g. in lieu of transmitting the information via a second interface which is available prior to the first interface becoming available.

Method, apparatus and system for determining an interface during a power state transition

Embodiments of the present invention provide a method and apparatus for detecting an interruption in memory initialization. A status bit for indicating whether memory initialization was interrupted or not is stored in a register. A basic input/output system (BIOS) sets the status bit prior to initialization and clears the status bit after initialization. The status bit cannot be reset by a standard platform reset. In operation, as the system is reset or turned on and prior to initialization, the BIOS checks the status bit to detect possible improper memory initialization. When the status bit is set, the BIOS concludes that a memory initialization had not completed and thus might be incorrect. The BIOS then causes power to be cycled to memory and any other steps needed are taken to return the memory to a functional state.

Method and apparatus for detecting an interruption in memory initialization

Growing community of inventors

Folsom, CA, United States of America

William Knolla