Waferscale Integration, Inc.

William Kammerer

Yaron Slezak

Baruch R Friedlander

There is provided a memory array including columns of memory cells, source lines and bit lines. The memory array includes precharging apparatus which discharge selected source lines while pre-charging the array. Two embodiments of the pre-charging apparatus are provided. In both, the source lines are connected to a common bit line (CNBL) via groups of source pull-up transistors. The source lines are also connected to a source decoder. In one embodiment, the source decoder discharges selected ones of the disconnected source lines. In another embodiment, the source decoder both discharges selected ones of the disconnected source lines and connects the remaining disconnected source lines to the CNBL line.

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Mountain View, CA, United States of America

William Kammerer