Omnivision Technologies, Inc.

Aurora Systems, Inc.

Xerox Corporation

William K Zuravleff

Sunny Yat-san Ng

Kin Yip Kenneth Kwan

Andrea Nguyen

A novel method for driving a display having an array of pixels arranged in a plurality of columns and a plurality of rows includes the steps of defining a modulation period for a row of pixels, dividing the modulation period into a number of coequal time intervals equal to n times the number of rows in the array, receiving a multi-bit data word that indicates an intensity value, and updating the signal asserted on the pixel during a plurality of the time intervals such that the intensity value is displayed by the pixel. Note that n is an integer greater than zero. The method can be applied to all rows, which can be driven asynchronously. A display driver for performing the novel methods is also disclosed. The present invention facilitates driving the display at 100% bandwidth efficiency during each time interval in the modulation period.

Display device and driving method based on the number of pixel rows in the display

Display device and driving method facilitating uniform resource requirements during different intervals of a modulation period

Display device and driving method that compensates for unused frame time

Display device and driving method using multiple pixel control units to drive respective sets of pixel rows in the display device

A reflective LCD array () configured to minimize distortion in mirrors () thereof produced by attachment of a plurality of vias () to the mirrors (). The vias () electrically connect the mirrors () to a metal layer () having circuitry thereon associated with the mirrors (). The vias () are positioned equidistant about a center () of the mirrors () such that spacing of the vias () is generally equidistant from an X axis () and Y axis () of the reflective LCD array. The vias () are positioned such that such symmetry is retained even where circuitry associated with adjacent mirrors () is a reflected image copy of the reference mirror (). Where even spacing about either the X axis () or the Y axis () is not practical, the vias () are grouped near the center () of the mirror () along that axis such that the effect is that of there being only a single via () along such axis.

Mirror contact pattern for a display device

A reflective LCD array ( ) having a plurality of mirrors ( ) in a mirror layer ( ) of material layers ( ). Underlying the mirror layer ( ) are at least a second metal layer ( ) and a third metal layer ( ). The second metal layer ( ) and the third metal layer ( ) will each have a first plurality of power traces ( ) and ( ), arrayed such that the power traces ( ) and ( ) generally completely underlie a plurality of gaps ( ) between the mirrors ( ). The power traces ( ) are positioned such that the average voltage presented thereby is &frac12;(V0&plus;V1). This will generally prevent the buildup of a residual DC bias between the mirrors ( ) and an ITO layer ( ) which might otherwise cause the production of ions ( ) which could degrade the performance of and perhaps damage the reflective LCD array ( ).

Residual DC bias correction in a video imaging device

A reflective LCD array ( ) having a plurality of mirrors ( ) in a mirror layer ( ) of material layers ( ). Underlying the mirror layer ( ) are at least a second metal layer ( ) and a third metal layer ( ). The second metal layer ( ) and the third metal layer ( ) will each have a first plurality of power traces ( ) and ( ), arrayed such that the power traces ( ) and ( ) generally completely underlie a plurality of gaps ( ) between the mirrors ( ). The power traces ( ) are positioned to shield light ( ) from reaching a plurality of silicon junctions ( ) where traces on a poly layer ( ) intersect traces on a diffusion layer ( ).

Combined power routing and light shielding in an LCD array

Circuits for rendering according to the present invention are operable to function in either halftone mode or error diffusion mode. A pixel multiplexor selects between a rasterized unrendered pixel signal from an input rasterized unrendered datastream in halftone mode and an error diffusion adjusted pixel signal generated by error diffusion hardware in error diffusion mode. A memory stores the current error diffusion state signal and retrieves it as the previous error diffusion state signal during the processing of the appropriate pixel in the next scan line in error diffusion mode. A threshold multiplexor selects between an error diffusion threshold signal and a halftone threshold signal. In halftone mode, the memory is operable to retrieve a halftone threshold signal which is supplied to the threshold multiplexor. A read address generator provides a read address signal to the memory for indicating the memory location from which to read either the previous error diffusion state signal or the halftone threshold signal. The read address generator includes a read address multiplexor for selecting between an error diffusion read address signal and a halftone read address signal. The read address generator further includes a stride multiplexor for providing the selected stride signal. The stride multiplexor has at least two stride inputs which receive stride signals corresponding to the appropriate stride values for error diffusion mode and halftone mode. A reset multiplexor provides the capability to set the read address signal either to a predetermined starting read address signal value or to the next read address signal.

Halftone and error diffusion rendering circuits

A test method ( ) for testing a reflective LCD array ( ) and apparatus including a mirror read pass transistor ( ). In the reflective LCD array ( ) has a plurality of system cells ( ), wherein data is written to a mirror ( ). A measurement device ( ) which, in one embodiment is a mirror read pass transistor ( ) allows read back of voltage on the mirror ( ), thereby providing a measurable criteria for determining if the mirror ( ) a mirror electrical contact ( ) and associated driving circuitry such as a master cell ( ), a slave cell ( ) and an analog mux ( ) are properly connected and functioning.

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Mountain View, CA, United States of America

William K Zuravleff