Micron Technology Incorporated

Other

Texas Instruments Corporation

Innovative Silicon S.a.

Innovative Silicon Isi Sa

William K Waller

Warren M Farnworth

Eugene H Cloud

Leland R Nevill

Raymond J Beffa

Ray J Beffa

Huy Thanh Vo

Brent Keeth

Mirmajid Seyyedy

Lee R Nevill

Ward D Parkinson

Eric Carman

Adrian E Ong

Paul S Zagar

Kuo-Yuan Hsu

James P Rupp

Thomas E Nichols

Eugen H Cloud

An electrical connection enclosure cover plate for use during drywall installation, texturing and painting processes, may include a single and unitary body having a rectangular and planar outer wall adapted to be affixed to an existing electrical box. The outer wall has a plurality of pins extending outwardly from an anterior face thereof. The pins are statically situated at opposed corners of the anterior face, and suitably sized and shaped to penetrate through an existing dry wall. The body has a plurality of primary panels directly connected to a posterior face of the outer wall. The primary panels may be adapted to frictionally engage the existing electrical box. The body may be adapted to be detachably coupled to the existing electrical box such that the outer wall may be adapted to cover and shield a front opening of the existing electrical box from undesirable debris and fluids.

Cover plate for electrical enclosure box and associated method

A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, sense amplifier circuitry is relatively compact and pitched to the array of memory cells such that a row of data may be read, sampled and/or sensed during a read operation. In this regard, an entire row of memory cells may be accessed and read during one operation which, relative to at least architecture employing multiplexer circuitry, may minimize, enhance and/or improve read latency and read access time, memory cell disturbance and/or simplify the control of the sense amplifier circuitry and access thereof. The sense amplifier circuitry may include write back circuitry to modify or 're-store' the data read, sampled and/or sensed during a read operation and/or a refresh operation in the context of a DRAM array. Moreover, the data that has been read, sampled and/or sensed by the sense amplifier circuitry during a read operation may be modified before being written back to one or more of the memory cells of the selected row of the array of memory cells.

Sense amplifier circuitry and architecture to write data into and/or read from memory cells

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

System for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, sense amplifier circuitry is relatively compact and pitched to the array of memory cells such that a row of data may be read, sampled and/or sensed during a read operation. In this regard, an entire row of memory cells may be accessed and read during one operation which, relative to at least architecture employing multiplexer circuitry, may minimize, enhance and/or improve read latency and read access time, memory cell disturbance and/or simplify the control of the sense amplifier circuitry and access thereof. The sense amplifier circuitry may include write back circuitry to modify or 're-store' the data read, sampled and/or sensed during a read operation and/or a refresh operation in the context of a DRAM array. The sense amplifier circuitry of this embodiment restores and/or refreshes data in an entire row of volatile and/or destructive read type memory cells in parallel. This architecture may minimize, enhance and/or improve write back and read latency parameters, relative to at least architecture employing multiplexer circuitry. Also, data that has been read, sampled and/or sensed by the sense amplifier circuitry during a read operation may be modified before being written back to one or more of the memory cells of the selected row of the array of memory cells.

A memory device with a data path circuit having support in the sense-amp region for compression testing of the device. The data path circuit uses NOR logic compression to provide a scalable design which may be extended to large circuits.

Memory data path circuit

A delay locked loop for generating a replica clock signal synchronized to an externally generated clock signal comprises a succession of separately controlled delay lines. Each of the delay lines has different delay resolution.

Circuit and method for generating a local clock signal synchronized to an externally generated reference clock signal

A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row.

Device and method for repairing a semiconductor memory

Growing community of inventors

Garland, TX, United States of America

William K Waller