Netezza Corporation

Ikos Systems, Inc.

Thinking Machines Corporation

Ibm International Group Bv

William K Stewart

Foster D Hinshaw

David L Meyers

Sharon Miller

Raymond A Andraka

Thomas F Knight, Jr

Barry M Zane

Edward C Parish

Jon P Wade

Michael Sporer

Muralidhar R Kudlugi

Mark E Seneski

Charley Selvidge

Raymond J Andraka

Ken Crouch

Joshua D Marantz

Charlie Selvidge

A distributed data processing system executes database operations, and includes a first group of host processors and a second group of job processing units (JPUs). A software application for executing database operations executes in a distributed fashion with portions of the database application executing on at least one central database processor and other portions executing on the data storage processors. At least a portion of the database application is implemented within and/or coordinated by a communication process that is executing the communication protocol. The communication process implements a load balancing function in front of the host processors, the load balancing function directing individual transactions to selected processors so as to evenly distribute workload.

Field oriented pipeline architecture for a programmable data streaming processor

A technique for read error failover processing in a mirrored disk system such as a Redundant Array of Inexpensive Disks (RAID) system, where individual disk units perform Logical Block Address (LBA) remapping. A read error causes a disk controller to report an 'unrecoverable' read error to a RAID controller. After receiving this report of an unrecoverable read error, rather than simply switching over to a mirror, the RAID controller first checks to see whether the disk that caused the error can successfully reassign an LBA. In particular, the RAID controller can retrieve the data that was associated with the failed LBA from the mirror, and then write that data to the offending disk. Only if this process does not succeed is the offending disk then treated by the RAID controller as having failed sufficiently to require failover to the mirror.

Rapid regeneration of failed disk sector in a distributed database system

A programmable streaming data processor that can be programmed to recognize record and field structures of data received from a streaming data source such as a mass storage device. Being programmed with, for example, field information, the unit can locate record and field boundaries and employ logical arithmetic methods to compare fields with one another or with values otherwise supplied by general purpose processors to precisely determine which records are worth transferring to memory of the more general purpose distributed processors. The remaining records arrive and are discarded by the streaming data processor or are tagged with status bits to indicate to the more general purpose processor that they are to be ignored. In a preferred embodiment, the streaming data processor may analyze and discard records for several reasons. The first reason may be an analysis of contents of the field. Other reasons for record blocking may have to do with tagging records that are to be visible to particular users depending upon a series of concurrent transactions.

Intelligent storage device controller

A field oriented pipeline processor for a data engine that can be programmed to recognize record and field structures of data received from a source such as a mass storage device. The processor has an interface for receiving field-delineated data from a field parser. The field parser parses non-field delineated data from a streaming data source into field delineated data under instruction from an external processing unit. The pipeline processor receives a field delineated data stream and employs logical arithmetic methods to compare fields with one another, or with values otherwise supplied by general purpose processors to precisely determine which records are worth transferring to memory of the more general purpose distributed processors. The architecture of the data engine allows for the use of substitution tables, temporary registers, and a data string register to assist in the efficiency and accuracy of the data engine processing.

A technique for read error failover processing in a mirrored disk system such as a Redundant Array of Inexpensive Disks (RAID) system, where individual disk units perform Logical Block Address (LBA) remapping. A read error causes a disk controller to report an 'unrecoverable' read error to a RAID controller. After receiving this report of an unrecoverable read error, rather than simply switching over to a mirror, the RAID controller first checks to see whether the disk that caused the error can successfully reassign an LBA. In particular, the RAID controller can retrieve the data that was associated with the failed LBA from the mirror, and then write that data to the offending disk. The disk controller for that disk will then perform its standard LBA remapping, and write the data to a new, good sector. Only if this process does not succeed is the offending disk then treated by the RAID controller as having failed sufficiently to require failover to the mirror.

In a digital circuit, a method for avoiding a bus contention condition which results from an overlap of active phases of multiple bus drivers. The method avoids such bus contention condition by including holding amplifiers in the data bus and by turning on respective bus drivers only for durations sufficient to establish a data value on the data bus.

Method for avoiding bus contention in a digital circuit

A system and a method provide full visibility to each net of a design under modeling by saving states of the design during modeling and reconstructing waveforms at each net by logic evaluation using the saved states. In one embodiment, primary data input signals and memory output signals ('sample signals') are saved by a logic analyzer, and used in an emulator to generate state vectors from a state snapshot previously recorded. Data compression techniques can be applied to minimize storage requirements, and parallel evaluation of segments of waveforms can be achieved, since saved states for the entire period of interest are available for waveform reconstruction at the time of the logic evaluation.

Reconstruction engine for a hardware circuit emulator

A resistor circuit includes a resistance control circuit and at least one insulated gate field effect transistor. The resistance control circuit includes a control signal output element including a reference transistor for generating a resistance control signal in response to an internal control signal to maintain the reference transistor at a selected resistance value and a resistance value control element including a reference resistor for generating a circuit control signal for controlling the resistance value of the reference transistor in relation to the resistance value provided by the reference resistor. The field effect transistor is controlled by the resistance control signal to provide a resistance value which is a function of the resistance value of the reference transistor (and therefore of the reference resistor) and ratios of selected physical characteristics of the reference transistor.

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Lexington, MA, United States of America

William K Stewart