Vlsi Technology, Inc.

William K Shu

Subhas Bothra

Stephen L Skala

Sang S Lee

Robert L Payne

Brian D Richardson

George Fujimoto

Richard L Groover

Carl H Fong

Dipu Pramanik

A semiconductor die assembly of this invention includes a lead system in which the leads are arranged in a radial pattern. That is, in a group of leads associated with a single side of a semiconductor die, leads which are furthest from the middle are most angled from the perpendicular. The semiconductor die includes an outer row of bond pads which are located proximate to the edge of the semiconductor die and an inner row of bond pads, parallel to the first row and located toward the interior of the semiconductor die surface. In one embodiment, one of the rows of bond pads is regularly spaced, while the other row of bond pads is variably spaced. The bond pads of the variably spaced row are positioned such that a bond wire which connects a bond pad of the inner row to its associated lead will pass substantially medially between the centers of the two closest bond pads of the outer

Staggered pad array

Disclosed is a semiconductor chip and method for making a semiconductor chip having strategically placed composite metallization. The semiconductor chip includes a topmost metallization layer that defines a plurality of patterned features including a plurality of input/output metallization pads for receiving an associated plurality of gold bonding wires. An inter-metal oxide layer that is defined under the topmost metallization layer. The semiconductor chip further includes an underlying metallization layer that is defined under the inter-metal oxide layer in order to electrically isolate the topmost metallization layer from the underlying metallization layer. The underlying metallization has a plurality of patterned features, and portions of the plurality of patterned features lie at least partially in locations that are underlying the plurality of input/output metallization pads. The portions of the plurality of patterned features are composite metallization regions that have a plurality of deformation preventing oxide patterns that are resistant to compression force induced plastic deformation that occurs when the plurality of gold bonding wires are applied.

Composite metallization structures for improved post bonding reliability

A universal semiconductor interconnect test structure and method for using the test structure is provided for detecting the presence of electrical open or short circuits within the test package. In one embodiment, the test structure comprises a layer of electrically non-conductive substrate and a bonding layer of electrically conductive material over the substrate layer. In a second embodiment, the universal test die comprises a layer of electrically non-conductive substrate and a pattern of electrically conductive material over the substrate layer, wherein the pattern forms a continuous array of individual bonding areas, each of the bonding areas being electrically isolated from adjacent bonding areas by a gap, and wherein the effective pitch of the bonding areas is not more than 25 microns. The universal test die of the present invention is suitable for developing wire bond and mold processes for all pad pitches, all pad layout designs, all package types, and all pin counts. The test die of the present invention greatly accelerates fine pitch development and avoids the burden of multiple test die inventory control. Additionally, the test die of the present invention simplifies wire bond programming and test program development.

Universal test die and method for fine pad pitch designs

An integrated-circuit package assembly includes a separate silicon substrate to which an integrated-circuit die is fixed. The separate silicon substrate serves as a heat spreader for the integrated-circuit die. The separate silicon substrate to which the integrated-circuit die is fixed is packaged in either a molded package body or a cavity-type package body. For the molded package body, the package body is molded around a leadframe, the integrated-circuit die, and the separate silicon substrate to which the integrated-circuit die is fixed. For a molded package body, the leadframe has bonding fingers formed at the inward ends thereof which are attached to the separate silicon substrate or the lead frame may have a die-attach pad to which is fixed the separate silicon substrate. For the cavity-type package, the package body includes a mounting surface formed adjacent to a cavity formed therein and the mounting surface has the separate silicon substrate fixed to the top surface thereof. The cavity-type body is formed of a ceramic material or as a multi-layer printed-circuit board. One or more interposer areas are formed on the top surface of the silicon substrate for attachment of connection wires from the integrated-circuit die or the leadframe. A portion of the interposer can extend between the integrated circuit die and the top surface of the silicon substrate to accommodate integrated-circuit dies of various sizes. The interposer includes a layer of oxide formed on the surface of the silicon substrate, which layer of oxide is covered with a layer of conductive material.

Electrically and thermally enhanced package using a separate silicon

A process for forming a stress relief layer on a semiconductor die and the resulting structure of the process is described. The stress relief layer is formed on a surface of a die which has already been attached to a die attach pad of a lead frame by a cured epoxy. The purpose of the layer is to act as a stress relief buffer by relieving the die surface from contraction forces created by a plastic material used for encapsulating the die and die attach pad portion of the lead frame, as the plastic material cools following hot injection molding of the material to form the encapsulation. Prior to application of the stress relief material onto the surface of the die, the surface is cleaned to restore its high surface energy. The stress relief material is formed by diluting a silicone compound with a non-reactive diluent such as a silicone oil so that both the surface energy and viscosity of the silicone compound is reduced. Following application of the stress relief material onto the surface of the semiconductor die, the applied layer is cured and as a consequence, the non-reactive diluent evaporates out of the applied stress relief layer.

Method of packing an IC die in a molded plastic employing an ultra-thin

A novel test die is disclosed for use in conjunction with a semiconductor assembly machine or process. The test die includes a plurality of sets of bond pads having different bond pad pitches which permits testing of those pitches with use of a single die. Bond pads suitable for array bonding and having different bond pad pitches are also disclosed. Electrical connections are provided between bond pads and permit detection of open and short circuits or other circuit defects. A staggered arrangement of bond pads permits bond pads to be packed more densely on the die. A method for fabricating a wafer having a plurality of bond pads which form a repeating pattern is given. The patterned wafer may be cut to form a test die having bond pads which are positioned to provide bond pad pitches as required by a user.

Growing community of inventors

Sunnyvale, CA, United States of America

William K Shu