Texas Instruments Corporation

Other

William K McDonald

Stephen Arlon Meisner

Adrian Salinas

Scott Alexander Johannesmeyer

Philip M O'Larey

Robert Paul Luckin

In examples, a method of manufacturing an integrated circuit comprises locating a photomask between a light source and a semiconductor wafer having a photoresist layer in a wafer scribe lane of the wafer, wherein the photomask comprises: a first mask scribe lane pattern; a second mask scribe lane pattern matching the first mask scribe lane pattern; and at least one circuit pattern of the integrated circuit located between the first and second mask scribe lane patterns. The method further includes illuminating the photomask to produce in the photoresist layer of the wafer scribe lane a first exposed portion corresponding to the second mask scribe lane pattern; locating the first mask scribe lane pattern between the light source and the first exposed portion; and illuminating the photomask, wherein the first mask scribe lane pattern substantially shields non-exposed portions of the photoresist layer of the wafer scribe lane from light exposure.

Integrated circuit with scribe lane patterns for defect reduction

A method of making a porous plug suitable for use as a phase separator, heat exchanger tube, wherein very small uniform holes are produced in a matrix by placing a first material in a matrix of a second material to form a bundle or billet comprising said materials, reducing the cross-section of the bundle or billet by drawing or extrusion to form a reduced cross-section rod, and then etching away one of the materials to leave a matrix with very small uniform holes therein. The reduced rod may be bundled with other similarly reduced rods to form a bundle which is again drawn to further reduce the cross-section thereof.

Method of making a foraminous article

A first polysilicon layer (18) is initially deposited onto a layer of field oxide (16). A dielectric (26) is formed on a portion of the first polysilicon layer (18). A second polysilicon layer (28) is deposited over the dielectric (26) and the first polysilicon layer (18). After the selective deposition of a mask (30) on to the second polysilicon layer (28), the polysilicon layers (18, 28) are anistropically etched to form a polysilicon to polysilicon capacitor (34) and a contact (36) of the capacitor (34). The dielectric (26) functions as an insulator for the capacitor (34) and as a barrier during anisotropic etching for protecting the underlying polysilicon layer (18).

Method for forming a polysilicon to polysilicon capacitor and apparatus

Method for forming a polysilicon to polysilicon capacitor

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Plano, TX, United States of America

William K McDonald