Vlsi Technology, Inc.

William K Hilton

Charles R Rimpo

Walter H Potts

James B Nolan

Albert J Weidner

An apparatus dynamically decodes memory addresses while supporting memory map options that require different memory bits which are dependent upon the memory address. A current CPU address or an address stored in an expanded memory specification (EMS) register is selected as the defining address. This defining address is then decoded by one of twenty-five (25) memory map options available. The resultant decoded signal drives select lines of a multiplexer whose output drives memory address lines to on-board banks of DRAMS.

Dynamic memory address line decoding

A full set of 36 EMS registers is provided for a computer, without using any of the registers located in the 256K to 640K address range of the standard RAM. This is accomplished by providing first and second alternate RAM sets of 12 registers each, which are accessed in the same 768K to 960K space as the standard twelve registers located in the 768K to 960K space. Access to the 24 registers in the first and second alternate sets of registers is controlled by two control bits. These bits translate address signals directed to the 768K to 960K space to be directed to one or the other of the first and second alternate sets of 12 registers; so that the alternate registers are accessed in the same space as the standard 12 registers in this 768K to 960K space.

Programmable control of EMS page register addresses

Apparatus for providing a boundary between on-board CPU memory and slot bus (EMS) memory is disclosed. A programmable comparator compares the CPU address with a pre-determined address in order to permit the memory array to be accessed by the CPU address or the EMS register, thus preventing the same memory array from being accessed by both the CPU address and the EMS register.

Programmable boundary between system board memory and slot bus memory

Apparatus for decoding and comparing memory addresses which determines DRAM size and interleave options utilized is disclosed. A row address and bank select bits are decoded and latched and are subsequently compared with the address during the next memory cycle. If the next address matches the address stored in the latch, a 'page hit' occurs and the memory cycle is shortened since the addresses during the consecutive memory address will differ only in the column address.

Page mode comparator decode logic for variable size DRAM types and

A method and apparatus for encoding expanded memory specification addresses and the bankselect signals associated therewith is disclosed. A 13th bit is provided and stores information as to the bankselect for the 12 bits of the expanded memory specification address. When the expanded memory specification register is accessed, the foregoing 13th bit is also retrieved and decoded to provide the proper bankselect decode signal.

Look-ahead circuit for fast decode of bankselect signals in EMS systems

A hardware system provides a programmable method for addressing expanded memory specification (EMS) registers in a personal computing system functioning with an MS-Dos.RTM. operating system or the like. The system provides hardware flexibility for addressing EMS registers at different addresses than the standard LIM EMS specification calls for, to permit utilization of register addresses in otherwise unavailable locations. The address translations are effected through hardware; so that no additional delays in the circuit operation occur.

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Phoenix, AZ, United States of America

William K Hilton