Delphi Technologies, Inc.

Delco Electronics Corporation

William Joseph Hulka

Seyed R Zarabadi

Mark Russell Keyse

Edward H Honnigford

Pedro E Castillo-Borelly

A DC offset compensation circuit (,) for compensating for a DC offset voltage of a signal amplifier (,) includes a first sample and hold circuit (,) having an input receiving an amplifier output signal (VOUT,) and an output supplying the sampled and held output signal (VOUT,) to a non-inverting input of a comparator,A first digital-to-analog (D/A) circuit (,) is responsive to a number of digital input signals to produce an analog DC target signal at an output (V,) thereof. The analog DC target signal is provided to an input of a second sample and hold circuit (,) having an output supplying the sampled and held analog DC target signal to an inverting input of the comparator,The output of the comparator,is provided to an offset cancellation control circuit (,) including a state machine (,) and a counter circuit (,) operable to modify a count value (OFFDAC) thereof depending upon statuses of a number of input control signals (CLK,CLK,STRT, STP) and the comparator output signal (CO). A second D/A circuit has a number of digital inputs receiving the count value (OFFDAC) and producing at an output (VDCO) thereof an analog DC compensation signal corresponding thereto. The analog DC compensation signal is provided to a input (VDCO) of the signal amplifier (,) to thereby force the DC component of the amplifier output signal (VOUT,) near the analog DC target signal, thereby minimizing an aggregate DC offset voltage attributable to the signal amplifier (,).

DC offset compensation circuit for a signal amplifier

An apparatus for providing an EEPROM programming signal, comprises a charge pump circuit for receiving a programming input signal on a programming input line and for charging up a gate drive voltage signal in response to a rising edge of the programming input signal. A transistor that includes a gate coupled to the gate drive signal couples the programming input line to a programming output line, which is coupled to an EEPROM. A ramp control circuit including (i) a capacitor and (ii) a transistor controlling the flow of current through the capacitor, is coupled to the programming output line for regulating a ramp-up rate of a programming output signal on the programming output line. A ramp-down circuit is coupled to the programming input line and to the programming output line and is responsive thereto for providing a ramp-down of the programming output signal after the programming input signal goes low.

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Kokomo, IN, United States of America

William Joseph Hulka