International Business Machines Corporation

William Jon Schmidt

Robert Ralph Roediger

Michael K Gschwind

Cary Lee Bates

Edward Curtis Prosser

Jin Song Ji

Ronald Ian McIntosh

Robert John Donovan

Bilha Mendelson

Vita Bortnikov

Roy N Bar-Haim

Nava Arela Aizikowitz

Inbal Shavit-Lottem

John Matthew Santosuosso

Gary Ross Ricard

Ulrich Weigand

Steven Jay Munroe

Daniel Rodman Hicks

Marc Noel Blais

Peter Jerome Steinmetz

Scott Thomas Robinson

Mark Novick

Liviu Asnash

Alan David Modra

Steven R Kunkel

Mark Robert Funk

Scott Patrick Hanson

Mikko Herman Lipasti

Orit Edelstein

James Albert Kryka

Joseph Patrick Reynolds

David John Lambert

Roger Wayne Southwick

Mircea Namolaru

Paul Lu Verne Godtland

Sherri Lynn McMeeking

Robert Ralph Roedinger

A compiler and linker include multiple addressing mode resolvers that generate code to resolve a plurality of function calls that use different addressing modes. A first addressing mode is defined where a first address for first data is specified as an offset from a base pointer. A second, relative addressing mode is defined where a second address for second data is specified as an offset from an address of an instruction that references the second data. The generated code assures correct operation when functions with different addressing modes are included in the computer program. The generated code preserves a base pointer when executing a function that uses relative addressing, when needed. The compiler inserts one or more relocation markers that trigger certain functions in the linker. A linker resolves the relocation markers inserted by the compiler, and generates code, when needed, that handles a mismatch between addressing modes.

Generating code for function calls that use multiple addressing modes

An optimizing compiler includes a vector optimization mechanism that optimizes vector operations that are reformatting-resistant, such as source instructions that do not have a corresponding reformatting operation, sink instructions that do not have a corresponding reformatting operation, a source instruction that is a scalar value, a sink instruction that may produce a scalar value, and an internal operation that depends on lanes being in a specified order. The ability to optimize vector instructions that are reformatting-resistant reduces the number of operations to improve the run-time performance of the code.

Compiler optimizations for vector operations that are reformatting-resistant

Techniques are disclosed for managing vector element ordering. One technique includes setting one or more control bits that determine a vector element ordering and a vector element numbering, where the one or more control bits are stored in a machine status register or in a page table entry. The vector element ordering includes one of a big-endian mode and a little-endian mode, and the vector element numbering includes one of a big-endian mode and a little-endian mode. The technique includes reading the one or more control bits to determine a big-endian or a little-endian mode for the vector element ordering and for the vector element numbering. The technique also includes performing a vector operation in the determined mode for the vector element ordering and the determined mode for the vector element numbering.

Independent vector element order and memory byte order controls

A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a bi-endian environment, wherein the processor architecture contains instructions with an inherent endian bias, along with at least one memory access instruction with a contrary endian bias. The compiler uses a code generation endian preference that matches the inherent computer system endian bias. The compiler generates instructions for vector instructions by determining whether the vector instruction has an endian bias that matches the code generation endian preference. When the endian bias of the vector instruction matches the code generation endian preference, the compiler generates one or more instructions for the vector instruction as normal. When the endian bias of the vector instruction does not match the code generation endian preference, the compiler generates instructions that include one or more vector element reverse instructions to fix the mismatch.

Compiler method for generating instructions for vector operations in a multi-endian instruction set

Techniques are disclosed for managing vector element ordering. One technique includes receiving an assembler command from a source file, wherein the assembler command indicates a vector element order for one or more subsequent machine instructions in the source file. The technique includes determining whether the vector element order comprises a big-endian (BE) order or a little-endian (LE) order. If the vector element order comprises a BE order, the technique includes assembling one or more subsequent machine instructions and placing the machine instructions in a BE section of a file. If the vector element order comprises a LE order, the technique includes assembling one or more subsequent machine instructions and placing the machine instructions in a LE section of the file.

An optimizing compiler includes a vector optimization mechanism that optimizes vector instructions by eliminating one or more vector element reverse operations. The compiler can generate code that includes multiple vector element reverse operations that are inserted by the compiler to account for a mismatch between the endian bias of the instruction and the endian preference indicated by the programmer or programming environment. The compiler then analyzes the code and reduces the number of vector element reverse operations to improve the run-time performance of the code.

Compiler optimizations for vector instructions

A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a bi-endian environment, wherein the processor architecture contains instructions with an inherent endian bias. The compiler uses a code generation endian preference that is specified by the user, and that determines a natural element order. When the compiler processes a computer program, it generates instructions for vector operations by determining whether the vector instruction has an endian bias that matches the specified endian preference. When the vector instruction has no endian bias, or when the endian bias of the vector instruction matches the specified endian preference, the compiler generates one or more instructions for the vector instruction as it normally does. When the endian bias of the vector instruction does not match the specified endian preference, the compiler generates instructions to fix the mismatch.

Compiler method for generating instructions for vector operations on a multi-endian processor

An optimizing compiler includes a vector optimization mechanism that optimizes vector instructions by eliminating one or more vector element reverse operations. The compiler can generate code that includes multiple vector element reverse operations that are inserted by the compiler to account for a mismatch between the endian bias of the instruction and the endian preference indicated by the programmer or programming environment. The compiler then analyzes the code and reduces the number of vector element reverse operations to improve the run-time performance of the code. The compiler generates a debugger table that specifies which instructions have corresponding reformatting operations. A debugger then uses the debugger table to display contents of the vector register, which is displayed in regular form as well as in a form that is reformatted according to information in the debugger table.

Debugger display of vector register contents after compiler optimizations for vector instructions

A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a bi-endian environment, wherein the processor architecture contains instructions with an inherent endian bias. The compiler uses a code generation endian preference that is specified by the user, and that determines a natural element order. When the compiler processes a computer program, it generates instructions for vector operations by determining whether the vector instruction has an endian bias that matches the specified endian preference (i.e., the inherent element order of the vector instruction matches the natural element order). When the vector instruction has no endian bias, or when the endian bias of the vector instruction matches the specified endian preference, the compiler generates one or more instructions for the vector instruction as it normally does. When the endian bias of the vector instruction does not match the specified endian preference, the compiler generates instructions to fix the mismatch.

Compiling source code to reduce run-time execution of vector element reverse operations, includes: identifying, by a compiler, a first loop nested within a second loop in a computer program; identifying, by the compiler, a vector element reverse operation within the first loop; moving, by the compiler, the vector element reverse operation from the first loop to the second loop.

Compiling source code to reduce run-time execution of vector element reverse operations

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Rochester, MN, United States of America

William Jon Schmidt