Intel Corporation

Other

Compaq Information Technologies Group, L.p.

William Johnson Bowhill

Krishnakanth Venkata Sistla

Vivek Garg

John Joseph Browne

Ankush Varma

Chris MacNamara

Vasudevan Srinivasan

Ian M Steiner

Nagasubramanian Gurumoorthy

Venkatesh Ramamurthy

Nikhil Gupta

Corey D Gough

Ripan Das

Sujal A Vora

David P Lerner

Joseph M Sullivan

Efraim Rotem

Alon Naveh

Rakesh Kumar

Don Soltis

Satish Shrimali

Lokesh Sharma

Eric Fetzer

Min Huang

Reid James Riedlinger

Baskaran Ganesan

Christopher MacNamara

Daniel William Bailey

Richard B Watson, Jr

Shane Bell

Zhiguo Wang

Eric Dehaemer

Victor Peng

Nachum M Gavrielov

Joseph R Doucette

Nemanja Marjanovic

Rory Sexton

Vinod Ambrose

Jeffrey D Pickholtz

Reid J Reidlinger

Christopher Nolan

Padraic Agnew

Colin Hanily

Harjinder Hullon

Seow Fung Ooi

Yin-Lung Lu

Joseph Doucette

Seow Ooi

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

Configuration of base clock frequency of processor based on usage parameters

In an example, there is disclosed a demand scaling engine, including: a processor interface to communicatively couple to a processor; a network controller interface to communicatively couple to a network controller and to receive network demand data; a scaleup criterion; a current processor frequency scale datum; and logic, provided at least partly in hardware, to: receive the network demand data; compare the network demand data to the scaleup criterion; determine that the network demand data exceeds the scaleup criterion; and instruct the processor via the processor interface to scaleup processor frequency.

Data center power management

In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.

Apparatus and method to implement power management of a processor

A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

Managing power consumption in a multi-core processor

A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the dynamic capacitance of the processor such that the dynamic capacitance is within an allowable dynamic capacitance value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

A clock distribution system for a semiconductor device provides for both on-chip and in-package clock distribution via on-chip and in-package clock distribution networks. Each of these networks is selectively enabled depending on the mode of operation. Specifically, for wafer testing, the on-chip clock distribution network is selected. Thus, a probe tester need only provide a single clock source with conventional timing specifications to test the operation of the chip. In contrast, during normal operation, an in-package clock distribution network is enabled. In-package clock routing provides the lowest variation mode and thus, will result in the maximum clock frequency for the chip.

Dual on-chip and in-package clock distribution system

In a floating point addition or subtraction procedure two shift operations of the operand fraction may be required. The first shift operation, based on the difference between the operand exponent arguments, involves aligning one of the operand arguments so that the addition or subtraction procedure between the operand fractions can be performed. In order to complete the associated computations correctly, it is necessary to know if any of the fraction positions removed from the fraction by the shift operation include non-zero signals, i.e., the operation typically referred to as computation of the 'sticky' bit. The second important shift operation occurs after the addition or subtraction of the operand fractions has taken place. The interim resulting operand fraction must be normalized, i.e., a non-zero signal is placed in the most significant operand fraction bit position and the operand exponent argument adjusted accordingly. In order to accomplish this normalization, the position of the leading one (most significant non-zero) bit must be identified. The present invention utilizes a carry chain both for computing the 'sticky' bit information and for detecting the leading one in an operand fraction.

Apparatus and method for using a single carry chain for leading one

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Framingham, MA, United States of America

William Johnson Bowhill