International Business Machines Corporation

William John Wright

Amol Anil Joshi

Xin Zhao

Robert J Allen

Vasant B Rao

Eric A Foreman

Vladimir P Zolotov

Peter Anton Habitz

Jeffrey G Hemmett

Natesan Venkateswaran

Jerry D Hayes

John P Dubuque

David Bruce White

Christopher J Kiegle

Nilesh C Date

Embodiments relate to multi-cycle signal identification for static timing analysis. An aspect includes identifying, in a circuit under test, a multi-cycle signal, the multi-cycle signal having a longer period than a main clock signal of the circuit under test. Another aspect includes mapping a plurality of additional signals of the circuit under test onto the multi-cycle signal, the plurality of additional signals each having a shorter period than the multi-cycle signal. Yet another aspect includes performing static timing analysis of the circuit under test based on the multi-cycle signal.

Multi-cycle signal identification for static timing analysis

Methods and systems for determining timing constraint analysis of an integrated circuit (IC) may include defining a sequence of sample points for timing constraint analysis of an n&#xd7;n matrix, each sample point corresponding to a timing arc of the IC that includes data and reference slews; initially simulating extreme sample points of the matrix, according to the sequence, by substituting timing constraints from liberty files of the IC type for time values of the data slews and conducting a binary search for optimized timing constraints; and interpolating other sample points, according to the sequence, each of the other sample points having a starting bisection point that results from linear interpolation of the timing constraint analysis from adjoining sample points, which were simulated.

Methods and systems to reduce a number of simulations in a timing analysis

A statistical single library that includes on-chip variation (OCV) is created for timing and power analysis of a digital chip design. Initially, library values for all cells of a digital chip design, including ranges for environmental and process parameters, are subject to a statistical model to create statistical timing for the ranges of the parameters. A statistical timing tool is applied across the ranges of the parameters to determine statistical corners for delay and input power to a subset of cells. The statistically determined delay and input power to the subset of cells is entered into the statistical single library. Each delay of each statistical corner for the subset of cells is compared with a chip sign-off statistical delay requirement of a test macro.

Statistical single library including on chip variation for rapid timing and power analysis

A method for performing input/output (I/O) floor planning on an integrated circuit design is disclosed. User design data related to I/O circuit associated with each package pin is initially collected. The collected user design data is then sorted according to operating conditions. Next, an I/O behavioral model and a package model are chosen based on the sorted data. A simulation deck is dynamically built with appropriate operating conditions. Finally, a simulation is performed through a circuit simulator using the chosen I/O behavioral model and the operating conditions.

Method and apparatus for performing input/output floor planning on an integrated circuit design

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Colchester, VT, United States of America

William John Wright