International Business Machines Corporation

Globalfoundries Inc.

William John Starke

Guy L Guthrie

Derek E Williams

Jeffrey A Stuecheli

Ravi Kumar Arimilli

Lakshminarayana Baba Arimilli

James Stephen Fields, Jr

Leo James Clark

Phillip G Williams

Michael Steven Siegel

Hugh Shen

Benjiman L Goodman

Robert Alan Cargnoni

John Steven Dodson

Geraint M North

Charles Francis Marino

Praveen S Reddy

Naresh Nayar

Bartholomew Blaner

Robert H Bell, Jr

Sanjeev Ghai

John David Irish

David John Krolak

Bernard Charles Drerup

Stephen J Powell

Jeff A Stuecheli

Alexander Erik Mericas

Bradly George Frey

Kenneth Michael Valk

Paul Allen Ganfield

Thomas L Jeremiah

Balaram Sinharoy

Ramakrishnan Rajamony

Ronald Nick Kalla

Hung Qui Le

Hillery C Hunter

Jody B Joyner

Cathy May

Hien Le

David Michael Daly

Casper A Scalzi

Steven R Kunkel

David W Cummings

Frank Eliot Levine

Randal Craig Swanberg

Eric Eugene Retter

William Eric Hall

Sheldon Bernard Levenstein

Robert Sidney Blackmore

Jentje Leenstra

Guerney D H Hunt

Thomas R Puzak

Edward Hugh Welbon

Francis Patrick O'Connell

Alvan Wing Ng

Eric M Schwarz

Steven R Carlough

David S Levitan

Richard Loise Arndt

Florian Alexander Auernhammer

Hanhong Xue

Chulho Kim

Jason Frederick Cantin

Piyush Chunilal Patel

Jie Zheng

Robert Allen Drehmel

Curtis Carl Wollbrink

Douglas W Westcott

Wayne Melvin Barrett

Aaron Christoph Sawdey

John Barry Griswell, Jr

Yiftach Benjamini

Ramachandra Divakaruni

Alper Buyuktosunoglu

Warren Edward Maule

Daniel Mark Dreps

Luis Alfonso Lastras-Montano

James Allan Kahle

Bulent Abali

Joshua M Rubin

Kamal Kumar Sikka

Pak-kin Mak

James A O'Connor

Gregory William Alexander

Brian Mitchell Bass

Kenneth Lee Wright

Peter Kenneth Szwed

Donald W Plass

Lee Evan Eisen

William Evan Speight

Albert James Van Norstrand, Jr

Michael Raymond Trombley

Shashank Nemawarkar

Joseph L Temple, Iii

Scott Michael Willenborg

Joseph Gerald McDonald

Richard Nicholas

James Francis Mikos

Ross Boyd Leavens

Jason Nathaniel Dale

A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Hierarchical ring-based interconnection network for symmetric multiprocessors

A destination host includes a processor core, a system fabric, a memory system, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link, to a source host with which the destination host is non-coherent. The destination host migrates, via the communication link, a state of a logical partition from the source host to the destination host and page table entries for translating addresses of a dataset of the logical partition from the source host to the destination host. After migrating the state and page table entries, the destination host initiates execution of the logical partition on the processor core while at least a portion of the dataset of the logical partition resides in the memory system of the source host and migrates, via the communication link, the dataset of the logical partition to the memory system of the destination host.

Memory migration within a multi-host data processing environment

A method, system, and computer program product for local DRAM caching of storage class memory elements are provided. The method identifies a cache line with a cache address in a local dynamic random-access memory (DRAM). The cache line is compressed within the local DRAM to generate a compressed cache line and an open memory space within the local DRAM. A cache tag is generated in the open memory space and a validation value is generated in the open memory space for the compressed cache line. The method determines a cache-hit for the cache line based on the cache address, the cache tag, and the validation value.

DRAM caching storage class memory

In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.

Multifunction communication interface supporting memory sharing among data processing systems

A data processing system includes multiple processing units all having access to a shared memory system. A processing unit includes a lower level cache configured to serve as a point of systemwide coherency and a processor core coupled to the lower level cache. The processor core includes an upper level cache, an execution unit that executes a store-conditional instruction to generate a store-conditional request that specifies a store target address and store data, and a flag that, when set, indicates the store-conditional request can be completed early in the processor core. The processor core also includes completion logic configured to commit an update of the shared memory system with the store data specified by the store-conditional request based on whether the flag is set.

Completion logic performing early commitment of a store-conditional access based on a flag

A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.

Speculative bank activate dynamic random access memory (DRAM) scheduler

An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

Information handling system with immediate scheduling of load operations

An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit includes request logic that, responsive to receipt on the first communication interface of a translation entry invalidation request, issues to the accelerator unit via the second communication interface an invalidation request that identifies an entry in the effective address-based accelerator cache to be invalidated utilizing a host tag identifying a storage location in the real address-based directory.

Translation invalidation in a translation cache serving an accelerator

A snooper of a processing unit connected to processing units via a system fabric receives a first single bus command in a bus protocol that allows sampling over the system fabric of the capability of snoopers to handle an interrupt and returns a first response indicating the capability of the snooper to handle the interrupt. The snooper, in response to receiving a second single bus command in the bus protocol to poll a first selection of snoopers for an availability status to service a criteria specified in the second single bus command, returns a second response indicating the availability of the snooper to service the criteria. The snooper, in response to receiving a third single bus command in the bus protocol to direct the snooper to handle the interrupt, assigns the interrupt to a particular processor thread of a respective selection of the one or more separate selections of processors threads distributed in the processing unit.

Managing efficient selection of a particular processor thread for handling an interrupt

An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit. The request logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, provides a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.

Integrated circuit and data processing system supporting address aliasing in an accelerator

The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.

Multiple chip bridge connector

An integrated circuit for a coherent data processing system includes a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit via the second communication interface. A request response identifies a target of a corresponding memory access request utilizing a host tag specifying an entry associated with the target in the real address-based directory.

Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator

A system, a method, and a computer program product for secure memory implementation for secure execution of virtual machines are provided. Data is processed in a first mode and a second mode, and commands are sent to a chip interconnect bus using real addresses, wherein the chip interconnect bus transports a number of bits for the real addresses. A memory controller is operatively coupled to a memory component. A secure memory range is specified by using range registers. If the real address is detected to be in the secure memory range to match a memory component address, a real address bit is set. If the real address is in the memory address hole, a security access violation is detected. If the real address is not in the secure address range and the real address bit is set, the security access violation is detected.

Secure memory implementation for secure execution of virtual machines

Growing community of inventors

Austin, TX, United States of America

William John Starke