Motorola Corporation

Bandspeed, Inc.

William John Rinderknecht

John Y Morton

Anthony R Schooler

Yun H Kim

Lawrence Edwin Connell

Pallab Midya

Charles R Ruelke

David P Gurney

Antonio Torrini

Poojan Wagh

William J Roeckner

Efstratios Skafidas

Ben William Jones

Neil Patrick Kelly

Zhuan Ye

Eric Crawford

Mark William Benson

Kevin M Andrews

Mike Gibson

Michael Luther

Nestor Fesas

Benson Chau

John Jack Morton

Michael Casey Luther

Blaine Kohl

Ben Jones

A radio receiver () having a multi-state variable threshold automatic gain control (AGC) for fast channel scanning acquisition includes an amplifier () having an automatic gain control (AGC) for controlling the gain of a receiver analog signal. An analog-to-digital converter (ADC) () is used for converting the receiving analog signal to a digital signal while a digital signal processor (DSP) () operates to process the digital signal. A signal magnitude estimator () in an AGC controller () provides a signal strength estimate of the received signal. The AGC controller () then sets the receiver amplifier () for an open-loop AGC operational mode and sets a first threshold for triggering an interrupt service request (ISR). This ISR is provided the DSP () and the host processor () if a radio frequency (RF) signal is detected above a first threshold during a priority scan of a priority channel to minimize interruptions in audio during priority scan.

Radio receiver having a multi-state variable threshold automatic gain control (AGC) for fast channel scanning acquisition and mehtod for using same

A multiple access wireless communications architecture provides selective, simultaneous communications with wireless devices located in different sections of a spatial area around a communications apparatus referred to as 'sectors'. This includes communications between wireless devices in a single sector, between wireless devices in different sectors and between wireless devices and a wired network or wireless backhaul network. The wireless communications architecture generally includes two or more wireless antenna arrangements that are each configured to provide communications with wireless devices located in a particular sector. Each wireless antenna arrangement is further configured to determine whether signals are being communicated on a communications channel before transmitting on the communications channel. This may be implemented, for example, using a carrier sense or energy detection mechanism. Wireless devices within a sector may communicate on the same or different communications channels, depending upon the particular multiple access protocol employed. For example, TDMA or CSMA may be used to allow wireless devices in a sector to share communications channels. Communications channels may also be used simultaneously in different sectors by different wireless devices.

Multiple access wireless communications architecture

The invention provides a method for generating a code sequence. A code-generation instruction is received from memory. One or more control signals are determined based on the code-generation instruction. A code sequence is generated based on the control signals, a current state input, and a mask input.

Method and system for a programmable code generator

A method and apparatus for a pulse width modulated (PWM) signal ( ) is provided. The input is a digital signal which is a modulated signal ( ). In the illustrated form, the modulated input signal is either a PDM signal or a PCM signal. In one embodiment of the present invention a PCM to PWM converter ( ) includes correction of duty ratio circuitry ( ). The methodology used may include recursion on the values obtained after prediction, interpolation, and correction. The digital to analog conversion system ( ) uses a PDM to PWM converter ( ) which operates in an all digital domain and includes no analog circuitry.

Method and apparatus for generating a pulse width modulated signal

A method for performing timing synchronization between digital input data and a system clock in a communication device includes providing a system clock rate that is higher than a data clock rate and sampling the input data at intervals in the system clock periods within the data clock period. The method includes adjusting the timing between the digital input data and the system clock by either shortening the number of system clock periods and sampling intervals, or lengthening the number of system clock periods and sampling the input data at normal intervals and providing data insertion to fill one of the extra system clock periods, such that more data samples are provided in the data clock period.

Timing synchronization in a communication device

An unbuffered flip-flop includes feedback control circuitry providing adaptive control of the internal node during the transfer and latching phases of the flip-flop to prevent back-writing. A complementary pair of transmission gates controlled by the output node are included in the feedback path between an output buffer and a feedback buffer. As noise voltage variations and spikes alter the voltage on the output node, the charge transmittance of the transmission gates is weakened or shut off, thereby preventing the incorrect logic state from being driven by the feedback buffer through to the input of the flip-flop's output buffer and causing back writing. Because the transmission gate transistors are complementary, one transistor or the other will be operating in a transmissive state for each of the bi-stable states of the output buffer during static operation of the flip-flop. As will be appreciated, because only two extra transistors are needed, the present invention has improved performance while consuming very little silicon area, power, and adding almost no delay to the circuit.

Unbuffered latch resistant to back-writing and method of operation

Growing community of inventors

Austin, TX, United States of America

William John Rinderknecht