International Business Machines Corporation

Inetrnational Business Machines Corporation

William John Livingstone

Peter Anton Habitz

Paul Steven Zuchowski

Jeannie H Panner

Laura R Darden

Daniel Joseph Mainiero

David James Hathaway

Jason D Hibbeler

Juergen Koehl

Douglas Wayne Kemerer

Mark R Lasher

Jeanne Paulette Spence Bickford

Joseph Leonard Metz

Steven H Voldman

Eric A Foreman

Douglas Willard Stout

Daniel Nelson Maynard

Leon Jacob Sigal

Gregory M Schaeffer

Patrick Edward Perry

Brian A Worth

Amol Anil Joshi

Erich C Schanzenbach

Andrew D Huber

William F Pokorny

John E Barwin, Iii

James J Engel

Jason Chung

Debra K Korejwa

Jeannie Therese Panner

Philip S Homsinger

Daniel Nelson Mayuard

Jeannie Therese Harrigan Panner

Michael Timothy Trick

A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.

Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design

A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

Apparatus and computer program product for semiconductor yield estimation

A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.

Method to quickly estimate inductance for timing models

Methods of treating via obstructions during design rule checking. The method comprises examining the size of the via obstruction with respect to a minimum size and a minimum spacing constraint of a design rule. Based upon the comparison, a neighboring via count for a number of via shapes neighboring the via obstruction may be initialized to equal a positive integer. Based upon the comparison, the via obstruction may be represented with a plurality of smaller via shapes during design rule checking.

Methods for design rule checking with abstracted via obstructions

Forming of a statistical model for a set of independently variable parameters for analysis of a circuit design is disclosed. In one embodiment, a method includes establishing a timing model including delay and delay changes due to process parameter variations (Pi) that impact timing; selecting an element of the circuit design that dominates circuit delay in the timing model; determining a delay sensitivity of each of a set of derived process parameters (Vj) for the element that are linear combinations of the process parameter variations (Pi); and selecting only those derived process parameters with a high sensitivity for use in the statistical model. The invention simplifies the statistical model and reduces the number of calculations require for timing analysis. A method of performing a timing analysis using the simplified statistical model is also disclosed.

Forming statistical model of independently variable parameters for timing analysis

A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

Semiconductor yield estimation

Disclosed are embodiments of an interconnection array for a circuit. The interconnection array comprises a victim net that is positioned parallel to and adjacent to sections of multiple crossed aggressor nets, thereby, minimizing the exposure of the circuit to delay or false switching as a result of coupling capacitance. Also, disclosed are embodiments of an associated method of re-routing an interconnection array that incorporates identifying a victim net and at least two aggressor nets and crossing the aggressor nets so that sections of multiple aggressor nets are positioned parallel to and adjacent to the victim net in order to minimizes the impact of coupling capacitance on the victim net with minimal changes to the wiring environment.

Method for re-routing an interconnection array to improve switching behavior in a single net and an associated interconnection array structure

A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.

Method of automated design and checking for ESD robustness

An integrated circuit chip having at least one source pin and a plurality of sink pins. A wire segment connects the source pin to at least one of the sink pins and includes at least two segments where one of the segments is larger than the other where electromigration is likely to occur.

Semiconductor wiring technique for reducing electromigration

A computerized tool or method that calculates the capacitance and resistance of each global wire on the chip, one wire at a time. The invention steps along a track containing a wire segment, grid point by grid point, calculating the resistance and capacitance at that point. At each grid point it searches the neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire. The method delivers capacitance and resistance values for each process condition for a grid unit length of wire, given the wire type and 3 dimensional environment of the wire segment. The capacitance and resistance at a grid point along the wire are generally determined by one table lookup for wire types based on the surrounding environment. These values are added along wire segments to deliver accurate 3 dimensional capacitances and resistances. The invention can also provide for wires and spaces of various types and widths not provided for in the tables and for calculation of net to net coupling capacitances.

Three dimensional track-based parasitic extraction

A wiring design tool which detects minimum area vias and replaces them with redundant vias pairs. The invention uses the definitions for single vias and tracks in a grid coordinate system and a file describing the design wires and their interconnections to select the most favorable direction for the placement. The invention accomplishes this by examining the directions one track away from each single via at various levels and according to the methodology of this invention, detects a possible situs for a redundant via pair, preferably where a segment of wire on the same net already exists. If no design rule violation occurs the system replaces the single via with a redundant via pair.

Redundant vias

A method for wiring IC chips such that electromigration criteria are met while minimizing the effect on overall chip wireability. A technique to optimize the width of automatically routed wire segments so that these widths are adequate to support the electromigration current on that net as a function of the capacitive loading of the net itself.

Wiring design tool improvement for avoiding electromigration by

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Unerhill, VT, United States of America

William John Livingstone