Yonsei University

Samsung Electronics Co., Ltd.

William Jinho Song

Jiwon Lee

Seongil O

Won Woo Ro

Chanho Park

Hyeonjin Kim

Youngin Kim

Bogil Kim

Taesoo Lim

Semin Koong

Disclosed are a DRAM cache system and an operating method thereof. The DRAM cache system includes a front-end module including a translation lookaside buffer (TLB) and a page table entry (PTE) and a back-end module, and the operating method includes checking, by the front-end module, the PTE when a TLB miss occurs in association with a memory request, calling, by the front-end module, a miss handler when a result of the checking the PTE is a tag miss, performing, by the front-end module, a tag update corresponding to the memory request through the miss handler, and offloading, by the front-end module, a cache-fill command to the back-end module.

DRAM cache system and operating method of the same

Provided is a control method of a deep neural network (DNN) accelerator for optimized data processing. The control method includes, based on a dataflow and a hardware mapping value of neural network data allocated to a first-level memory, calculating a plurality of offsets representing start components of a plurality of data tiles of the neural network data, based on receiving an update request for the neural network data from a second-level memory, identifying a data type of an update data tile corresponding to the received update request among the plurality of data tiles, identifying one or more components of the update data tile, based on the data type of the update data tile and an offset of the update data tile among the calculated plurality of offsets, and updating neural network data of the identified one or more components between the first-level memory and the second-level memory.

Deep neural network accelerator for optimized data processing, and control method of the deep neural network accelerator

A controller is provided. The controller creates a page table including page table entries including mapping information for translating a virtual address to a physical address. Each of the page table entries includes: a virtual page number, a physical frame number, valid information, and size information. The virtual page number is included in a virtual address, the physical frame number is included in a physical address, the valid information includes a first predetermined number of bits, and the size information includes a second predetermined number of bits. The first predetermined number of bits represents an address translation range in a page table entry or a number of page table entries to be grouped, and the size information represents a size indicated by each bit of the first predetermined number of bits.

Controller, computing system including the same, and method of creating and searching page table entry for the same

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Seoul, South Korea

William Jinho Song