National Semiconductor Corporation

Texas Instruments Corporation

William James McIntyre

Jeffrey P Kotowski

Nathanael Griesert

John Philip Parry

Aleksandar Prodic

Jeff Kotowski

Sombuddha Chakraborty

Alvaro Aguilar

Timothy McRae

Arun Rao

Gregory J Smith

Alexander Burinskiy

Mengzhe Ma

Damian Swank

Stephane Guenot

Florence Jacquet

An apparatus includes: a switched capacitor (SC) converter to generate a first voltage based on a voltage source; and a direct current-to-direct current (DC-DC) converter to generate a second voltage based on the voltage source of the apparatus. A difference between the first voltage and the second voltage corresponds to an output voltage.

High efficiency hybrid power converter apparatus

In methods, apparatus, systems, and articles of manufacture to a high efficient hybrid power converter, an example apparatus includes: a switched capacitor (SC) converter to generate a first voltage based on a voltage source; and a direct current-to-direct current (DC-DC) converter to generate a second voltage based on the voltage source of the apparatus, the difference between the first voltage and the second voltage corresponding to an output voltage.

Apparatus for a high efficiency hybrid power converter and methods to control the same

A circuit and method for charging a super capacitor to an optimal voltage that provides a desired flash diode current value while minimizing power dissipation in circuit elements other than the flash diode. One embodiment uses periodic sampling of the current through the flash diode and termination of the charging upon the super capacitor having been charged to a voltage value that produces the desired flash diode current. Another embodiment includes a current regulator in the flash diode firing circuit that keeps the current at a substantially constant level during the time that the flash diode is being fired.

Method and circuit for charging of super capacitor as energy source for flash diodes

A circuit and method for monitoring the forward voltage for a plurality of LEDs in a battery powered device so that the gain in the LED driver circuit can be switched at a point that optimizes the energy provided by the battery. The invention provides for sensing each LED's voltage, V, and determining the maximum forward voltage, V, between the plurality of LEDs. The invention uses the knowledge of Vin conjunction with V, converter output resistance and LED current, and current source/sink minimum headroom to switch from an initial gain to some higher gain just before the current sinks/sources would drop out, or from a higher gain to a lower gain in the event of the battery voltage going back to a voltage close to its initial value after being momentarily pulled down by a heavy load.

Forward LED voltage monitoring for optimizing energy efficient operation of an LED driver circuit

A switch array circuit that enables voltage regulation by bucking a relatively larger input voltage as it declines over time with different fractional gains that are based on different gain phase arrangements for a plurality of capacitors. A common rest phase is provided during the switching between the different gain phases. The rest phase inherently enables power to be conserved during gain transitions. Increasingly larger fractional gain phases (less buck) is provided as the input voltage declines over time, e.g., from &#x2153; to &#x2156; to &#xbd; to &#x2154; to unity, and the like. Also, the common rest phase for the plurality of capacitors is arranged to minimize fluctuation of the output voltage during switching between phases to generate a selected gain from the gain phase. Additionally, the common rest phase conserves/stores energy during switching transitions between multiple gain phases. The stored energy in the common rest phase can be subsequently reused in the gain phases.

Fractional gain circuit with switched capacitors and smoothed gain transitions for buck voltage regulation

A switched-capacitor type voltage regulator is provided. The regulator includes a flying capacitor and switches, including first and second transistors which operate as switches. The switches are arranged to operate such that the flying capacitor is coupled to an input voltage during a first phase, and switched to provide an output voltage during a second phase. During the first phase, the first transistor is employed to couple the capacitor to the input voltage, and a second transistor is employed to couple (the other side of) the capacitor to another node (e.g. Ground). Additionally, another switch is coupled between the gate and the drain of either the first transistor or the second transistor. Also, during the first phase, if the input voltage is greater than the output voltage, the other switch is closed so that the transistor that the other switch is connected to operates as a diode.

Apparatus and method for switch connected as a diode in a charge pump

A multi-stage transistor circuit is provided in which the multiple transistor stages are coupled in parallel and switched individually in sequence by a series arrangement of buffers. Each buffer drives the gate of a corresponding stage of the multi-stage transistor circuit with a gating signal that is delayed by each buffer. Optionally, the voltage of the gating signal can be varied. Each transistor stage may comprise one or more transistors in parallel. A switched capacitor DC/DC converter incorporating the multi-stage transistor circuit is provided in which parasitic ringing at the output is substantially reduced or eliminated. Additionally, the multi-stage transistor circuit is well suited for implementing an adaptive non-overlapping gating signal generator for complementarily driving a series arrangement of multi-stage transistors. An adaptive gating signal generator incorporating the multi-stage transistor circuit provides the minimum dead time between the gating signals that will ensure under all conditions that the multi-stage transistors will not be on at the same time.

Suppression of parasitic ringing at the output of a switched capacitor DC/DC converter

A switched capacitor array circuit for use in a voltage regulator, including L, M and N banks of capacitor positions disposed intermediate an input node and a ground node, between the input and output nodes and between the output node and the ground node, respectively. Switching circuitry operates to switch three capacitors between a common phase configuration and a gain phase configuration. Two of the capacitors are disposed in one of the L, M and N banks of capacitor positions, with the third capacitor being disposed in a different one of the L, M and N banks of capacitor positions in the common phase configuration. When switched from the common phase to the gain phase configuration, at least one of the three capacitors is moved to a different capacitor position.

Switched capacitor array circuits having universal rest state and method

A system and method for providing for on-chip configuration, control and testing of mixed signal circuitry within an integrated circuit. A dual signal interface conveys the serial data and clock signals used for controlling the enablement, disablement and operational modes of the synchronous circuitry responsible for such on-chip configuration, control and testing, thereby minimizing the amount of overhead, in terms of interface terminals needed, for providing such capability.

Apparatus and method for establishing a data communication interface to control and configure an electronic system with analog and digital circuits

A capacitor array circuit having at least two capacitors, switching circuitry coupled to the capacitors and to input, output and common nodes and control circuitry. The control circuitry operates to sequentially switch the array through three different states so that a voltage is developed across each of the capacitors which is at a fixed value proportional to a voltage present at the input node. The fixed and thus determinate voltage drop across each of the capacitors operates to define voltages at any nodes intermediate the capacitors thereby, among other things, insuring reliable operation of the capacitor array circuit.

Switched capacitor array circuit for use in DC-DC converter and method

A structure and process are provided for converting DC-DC voltages, which allows both buck and boost conversion utilizing a single switched capacitor array. In one embodiment of this invention, the switched capacitor array comprises multiple gain blocks, where the gain blocks are identical and stacked upon each other. The switches and capacitors are configured so that various combinations of series and parallel capacitor connections are possible, and thus both buck and boost conversions are attainable with one switched capacitor array. Other embodiments of the present invention use multiple gain blocks, configured such that the capacitor in each gain block can be connected to ground. As a result, a single charge state for a range of desired gains can be configured for use with a shared or common rest state, i.e., a capacitor configuration which is the same regardless of the desired gain. In the charge state, selected capacitors are configured in series for the desired gain setting, while in the shared rest state, all the capacitors are configured in parallel from the output to the input. Because a shared rest state is used, the correct charge is always transferred at the desired gain with a single switched capacitor array.

Buck and boost switched capacitor gain stage with optional shared rest state

A switched capacitor circuit, for use in voltage converters and the like, which includes a switched capacitor array, a plurality of MOS transistor switches and drive circuitry for controlling the state of the switches. The drive circuitry alternates between a first phase where at least one capacitor of the array is connected by the switches between an input node and an output node and a second phase where the capacitor is connected in series between one of the output and input nodes and a third node, such as a circuit common. Boost and buck gain configurations are achieved when connected to the output and input nodes, respectively. A voltage management feature is implemented to control voltages produced in the array so that no PN junction of the transistor switches formed by a body and the drain/source regions disposed in the body becomes forward biased.

Switched capacitor circuit having voltage management and method

A structure and method are provided for converting unregulated DC voltages to regulated DC voltages using pulse frequency modulation (PFM) and a switched capacitor array capable of multiple gains, where gain selection is based on the output voltage. The selected gain is maintained at or above a minimum gain determined from the input voltage. A regulated voltage, which is equal to or greater than a desired output voltage, is thus available to the load over a wider range of inputs and with greater conversion efficiency.

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Wheatland, CA, United States of America

William James McIntyre