Arm Limited

William James Deacon

Graeme Peter Barnes

Marc Zyngier

Catalin Theodor Marinas

Catalin Marinas

An apparatus comprises processing circuitry which has a hypervisor execution mode for execution of a hypervisor for managing one or more virtual processors executing on the processing circuitry, and at least one less privileged execution mode than the hypervisor execution mode. In response to a conditional yield to hypervisor instruction executed in the at least one less privileged execution mode, an instruction decoder controls the processing circuitry to determine whether at least one trap condition is satisfied, and when the at least one trap condition is determined to be satisfied, to switch the processing circuitry to the hypervisor execution mode; and store, in at least one storage element accessible to instructions executed in the hypervisor execution mode, at least one item of scheduling hint information for estimating whether the at least one trap condition is still satisfied.

Conditional yield to hypervisor instruction

An apparatus comprises address translation circuitry () to perform a translation of a virtual address () comprising a virtual tag portion () and a virtual address portion () into a physical address () comprising a physical tag portion () and a physical address portion (). The address translation circuitry comprises address tag translation circuitry () to perform a translation of the virtual tag portion into the physical tag portion and the address translation to be performed is selected in dependence on the virtual address.

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Cambridge, United Kingdom

William James Deacon