Nvidia Corporation

Massachusetts Institute of Technology

Rambus Inc.

Avici Systems, Inc.

Leland Stanford Junior University

Lsi Corporation

Future Wei Technologies, Inc.

Intel Corporation

Lsi Logic Corporation

Mips Technologies, Inc.

Arm Finance Overseas Limited

Other

Cray Incorporated

Sunpower Corporation

U.S. Department of Energy

William James Dally

John Wood Poulton

Philip P Carvey

Larry R Dennison

Stephen William Keckler

Brucek Kurdo Khailany

Thomas Hastings Greer

Ramin Farjad-Rad

Teva J Stone

Jonah Matthew Alben

William Frederick Mann, Iii

Joel S Emer

Carl Thomas Gray

Rangharajan Venkatesan

Scott W Rixner

P Allen King

Steven Lee Scott

Stephen G Tell

Larry Robert Dennison

Robert Gelinas

Sol Katzman

W Patrick Hays

Dennis Charles Abts

Thomas H Greer, Iii

Angshuman Parashar

Xiaoying Yu

Hiok-Tiaq Ng

Gregory M Waters

John J Kim

James Michael O'Connor

Sudhir Shrikantha Kudva

Nan Jiang

Yakun Shao

Gopalakrishnan Ramamurthy

Daniel K Hartman

Ujval J Kapasi

John H Edmondson

Robert E Palmer

Michael A Parker

Gopalakrishnan Meempat

Anjul Patney

Ilyas Elkin

Brian Matthew Zimmer

Nicholas P Carter

Andrew Joseph Ponec

Darren Hau

Jim Jian Lin

Miaorong Wang

Daniel Smith

John D Owens

Paul A Beliveau

Liang Chen

John Erik Lindholm

Raghunath Krishna Rao

Ephrem C Wu

Ge Yang

Christopher J Buehler

Jung Ho Ahn

Arjun Singh

Xiaojun Wang

Staffan Ericsson

Walker Joseph Turner

Jeffrey Michael Pool

Franciscus W Sijstermans

Matthew Rudolph Fojtik

David Tarjan

Daniel Robert Johnson

Donald A Priore

Mark Alan Gebhart

Benjamin Alexander Johnson

Mahmut Ersin Sinangil

DeForest Tovey

Jeffrey P Grossman

James David Balfour

Martin Braff

Ignacio Llamas Ubieto

Steve Haihang Dai

John J Owens

Jason Lavar Clemons

Sam Rosen

Ming-Ju Lee

Zhou Yan

Yuanzhi Hua

Daniel J M Maren

Andrew A Chien

Waldemar P Horwat

Stuart Fiske

Nathaniel Pinckney

Charbel Sakr

Vivek Choksi

Christopher Ling

Mattan Erez

G E (Francis) Yang

Daniel JM Maren

An on-chip network (NoC) is a critical component of a GPU, CPU, network switch, or accelerator. The network nodes may be arranged in a two-dimensional array with each network node coupled to neighboring network nodes vertically and horizontally, with or without diagonal connections. Conventional routers within network nodes are synchronous, taking from 1-10 clock cycles to determine an output port, arbitrate between virtual and physical channels, and account for credits. In contrast, in an embodiment, transmission of a packet between network nodes often occurs in less than one clock cycle because the handshake protocol and the circuitry are not synchronized using a clock signal. When implemented using asynchronous logic, the routing delay and power are reduced. The channel latency is the minimum time needed to drive the physical traces. Such an asynchronous NoC may reduce latency by a factor of two or more compared with a synchronous NoC.

Asynchronous on-chip network

Quantizing tensors and vectors processed within a neural network reduces power consumption and may accelerate processing. Quantization reduces the number of bits used to represent a value, where decreasing the number of bits used can decrease the accuracy of computations that use the value. Ideally, quantization is performed without reducing accuracy. Quantization-aware training (QAT) is performed by dynamically quantizing tensors (weights and activations) using optimal clipping scalars. 'Optimal' in that the mean squared error (MSE) of the quantized operation is minimized and the clipping scalars define the degree or amount of quantization for various tensors of the operation. Conventional techniques that quantize tensors during training suffer from high amounts of noise (error). Other techniques compute the clipping scalars offline through a brute force search to provide high accuracy. In contrast, the optimal clipping scalars can be computed online and provide the same accuracy as the clipping scalars computed offline.

Optimally clipped tensors and vectors

A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture includes multiple chips, each with a central processing element, a global memory buffer, and a plurality of additional processing elements. Each additional processing element includes a weight buffer, an activation buffer, and vector multiply-accumulate units to combine, in parallel, the weight values and the activation values using stationary data flows.

Efficient neural network accelerator dataflows

A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.

Hierarchical network for stacked memory system

Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components using an asynchronous accumulator to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. The sum may then be converted back into the logarithmic format.

Inference accelerator using logarithmic-based arithmetic

Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. The sum may then be converted back into the logarithmic format.

Neural network accelerator using logarithmic-based arithmetic

Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.

Application partitioning for locality in a stacked memory system

Asynchronous accumulator using logarithmic-based arithmetic

A method, computer program product, and system perform computations using a processor. A first instruction including a first index vector operand and a second index vector operand is received and the first index vector operand is decoded to produce first coordinate sets for a first array, each first coordinate set including at least a first coordinate and a second coordinate of a position of a non-zero element in the first array. The second index vector operand is decoded to produce second coordinate sets for a second array, each second coordinate set including at least a third coordinate and a fourth coordinate of a position of a non-zero element in the second array. The first coordinate sets are summed with the second coordinate sets to produce output coordinate sets and the output coordinate sets are converted into a set of linear indices.

Sparse convolutional neural network accelerator

When a signal glitches, logic receiving the signal may change in response, thereby charging and/or discharging nodes within the logic and dissipating power. Providing a glitch-free signal may reduce the number of times the nodes are charged and/or discharged, thereby reducing the power dissipation. A technique for eliminating glitches in a signal is to insert a storage element that samples the signal after it is done changing to produce a glitch-free output signal. The storage element is enabled by a 'ready' signal having a delay that matches the delay of circuitry generating the signal. The technique prevents the output signal from changing until the final value of the signal is achieved. The output signal changes only once, typically reducing the number of times nodes in the logic receiving the signal are charged and/or discharged so that power dissipation is also reduced.

Preventing glitch propagation

A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.

Scalable multi-die deep learning system

The disclosure provides processors that are configured to perform dynamic programming according to an instruction, a method for configuring a processor for dynamic programming according to an instruction and a method of computing a modified Smith Waterman algorithm employing an instruction for configuring a parallel processing unit. In one example, the method for configuring includes: (1) receiving, by execution cores of the processor, an instruction that directs the execution cores to compute a set of recurrence equations employing a matrix, (2) configuring the execution cores, according to the set of recurrence equations, to compute states for elements of the matrix, and (3) storing the computed states for current elements of the matrix in registers of the execution cores, wherein the computed states are determined based on the set of recurrence equations and input data.

Processor for performing dynamic programming according to an instruction, and a method for configuring a processor for dynamic programming via an instruction

Glitch-free multiplexer

Growing community of inventors

Stanford, CA, United States of America

William James Dally