Tandem Computers Incorporated

Hewlett-packard Development Company, L.P.

Compaq Computer Corporation, Inc.

William J Watson

William P Bunton

David P Sonnier

David J Garcia

Robert W Horst

John C Krause

William Edward Baker

Linda Ellen Zalzala

David Allen Brown

Richard W Cutts, Jr

Geoffrey I Iswandhi

Daniel L Fowler

William F Bruckert

Frank A Williams

John D Coddington

Susan S Meredith

Stephen G Low

Paul N Hintikka

Curtis Willard Jones, Jr

James Stevens Klecka

Gary F Campbell

David T Heron

David Sonnier

Melvin K Benedict

John Michael Brown

Douglas E Jewett

Steven C Meyers

Richard O Larson

Charles Edward Peet

Patricia L Whiteside

Randall G Banton

Boyd E Slade

David L Aldridge

Carl W Kagy

Robert B Mizell

David P Sonner

Wiliam P Bunton

David Joseph Kinkade

Stephen H Miller

Kenneth H Porter

Barry Lee Drexler

Harry Frank Elrod

Michael P Simpson

H David Mattson

Patracia L Whiteside

Adaptive sets of lanes are configured between routers in a system area network. Source nodes determine whether packets may be adaptively routed between the lanes by encoding adaptive control bits in the packet header. The adaptive control bits also facilitate the flushing of all lanes of the adaptive set. Adaptive sets may also be used in uplinks between levels of a fat tree.

System and method for configuring adaptive sets of links between routers in a system area network (SAN)

A link extender node is used to extend links between end nodes and/or routing nodes in a system area network. A connection includes a first link, coupling an end or routing node to a local port of a first link extender, a second link coupling the remote ports of first and second link extenders, and a third link coupling the local port of the second link extender to an end or routing node. The link extender includes link exception detection logic and transmits a this link bad command on the link generating the exception and transmits an other link bad command on the link not generating the exception.

Link extenders with error propagation and reporting

A link extender is used for extending links between end nodes or router nodes in a system area network. Nodes in the network transmit link alive symbols to indicate that a link is alive. The link extender includes a link alive propagation feature for propagating the loss of link alive between ports of the link extender.

Link extenders with link alive propagation

A biased arbitration technique utilizes a transpose table to arbitrate access to a shared resource. Each column of transpose table is a binary bias vector encoding a bias value assigned to one of the requestors. The rows of the table are fetched to assure that requestors having high bias values are granted more frequent access to the shared resource. A look-ahead feature skips rows having all zeros and an unbiased cycle that assures all requesting ports are serviced regardless of their bias values.

Transpose table biased arbitration scheme

A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requestor and responder nodes, coupled by a plurality of paths, that maintain the good and bad status of each path and also maintain local copies of a message sequence number. If an error occurs for a transaction over a given path, the requestor informs the responder, over a good path, that the given path has failed and both nodes update their path status to indicate that the given path is bad. A barrier transaction is used by the requestor to determine whether the error is transient or permanent, and, if the error is transient, the requestor retries the transaction.

System and method for implementing error detection and recovery in a system area network

An improved hybrid flow control protocol for providing FIFO capacity to prevent overflow due to bytes arriving after the FIFO indicates it is not ready to receive any more bytes utilizes a combination of a high/low watermark and credit based system. In one embodiment, when the byte count exceed the high watermark fixed credits are sent when N bytes are pulled from the FIFO. In a second embodiment, variable credits are sent depending on the difference between the number of bytes received in and pulled from the FIFO.

Hybrid flow control

Self-checked, lock step processor pairs

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Method of data communication flow control in a data processing system

Detecting and isolating errors occurring in data communication in a

A multiple processing system, comprises at least a pair of processor units communicatively connected to a number of peripheral devices through a network that includes routing devices interconnected to route information in the form of message packets sent between the processor units and peripheral devices. Data describing the topographical interconnections of the system elements is maintained with the system. A service processor accesses the data, determines therefrom the topographical interconnections forming the network, assigns addresses/identifications to the system elements, and configures the router devices to establish the most direct routes between system elements for message packets sent on the network.

Method and apparatus for configuring routing paths of a network

A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination of the message, and may also contain requests to write to, or read from, storage of a CPU. Protection against errant reads or writes is provided by an access validation method that utilizes access validation information contained in plural entries maintained by each CPU. Each entry provides validation by identifying what elements of the system has read and/or write wccss to the memory of that CPU, without which memory access is denied.

Storage access validation to data messages using partial storage address

A processing system includes multiple processor units and multiple input/output elements communicatively interconnected by a system area network having a plurality of multi-ported router elements. Communication between the system elements uses message packets that contain, among other things, destination information that identifies the intended recipient of the message packet. That destination information is used, at least in part, for routing message packets from a its source to its intended destination. Deadlocks are eliminated by providing each router with information as to which ports cannot be used for re-transmission of a message packet, depending upon which port is receiving that message packet.

Network message routing using routing table information and supplemental

A DC power distribution system can be configured to utilize a variable number of AC power distribution units. Installation of a converter unit in place of a PDU and resetting of associated switches permits inexpensive and rapid reconfiguration of the system without interrupting power supply to current receiving units. Techniques such as mechanical keying and sense switches minimize the possibility of human error in the reconfiguring operation.

Flexible implementation of distributed DC power

Apparatus for detecting divergence between a pair of duplexed,

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Fail-fast, fail-functional, fault-tolerant multiprocessor system

Growing community of inventors

Austin, TX, United States of America

William J Watson