Lsi Logic Corporation

Lsi Corporation

William J Schmitz

Mark Slutz

William W Voorhees

Erik Paulsen

David W So

Gabriel Leandro Romero

Jeffrey K Whitt

David T Uddenberg

Andrew Hadley

Keith Grimes

Adam S Browen

Raymond S Rowhuff

Gregory William Achilles

Stuart L Nuffer

Gordon Keith Grimes

John Grabarek

Methods and systems assess timing of PCI signals. A test mode is initiated within a host adapter board. A clock signal is generated for the host adapter board. PCI signals are generated within the host adapter board. One or more PCI signal lines of the host adapter board are electronically selected; and timing (e.g., slew rate and/or clock-to-signal valid) of the one or more PCI signal lines is assessed.

Systems and methods for assessing timing of PCI signals

Systems and methods for analyzing data passing between an SAS/SATA device and a plurality of other devices are presented. A system includes a plurality of physical interfaces configured for passing data between the SAS/SATA device and the other devices. The system also includes a test interface, or test PHY, configured for coupling to the physical interfaces for analysis of the data passing through those physical interfaces. The test PHY may be integrally configured with the SAS/SATA device and may substantially minimize alteration of characteristic impedance caused by external analysis of the data. The system may also include a multiplexer for selectively coupling the PHYs to the test PHY.

Systems and methods for analyzing data of a SAS/SATA device

A system and method for testing the signals on a parallel communication bus uses a single printed circuit board that connects to the bus. The signals from the bus may be passively and actively filtered prior to a multiplexer. The multiplexer may be controlled by a variety of inputs, including communications over a second bus by a remote device. The output of the multiplexer is one or more probe points that may be connected to a measurement device.

Parallel bus debugging tool

A method for populating and depopulating components of negligible impedance facilitates the testing of circuit boards. The test circuitry may be formed upon the circuit board under test. Testing may be performed with great accuracy for the time between the triggering edge of a clock pulse and a resulting valid signal change. Slew rates of bus signals may be more easily measured.

Methodology to accurately test clock to signal valid and slew rates of PCI signals

A method and apparatus for generating a CRC (cyclic redundancy check)/parity error in network environment. A SCSI (small computer systems interface) bus expander such as an Ultra320 bus expander or the like is added between a sending device and a receiving device. The sending device-receiving device pair may execute a training session to determine the skew compensation. During the training session, the SCSI bus expander may figure out timing differences due to skew and adjusts the timing of each data signal to compensate for skew. For each data signal, a compensated time may be obtained. The compensated time may then be modified through a JTAG (Joint Test Action Group) port of the SCSI bus expander. The compensated times may be adjusted such that a CRC/parity error is generated on every I/O (input/output) or just some I/Os to the receiving device. By intentionally generating a CRC/parity error, the response of the devices in the SCSI environment to a CRC/parity error may be evaluated during an input/output (I/O) test.

Method and apparatus for generating CRC/parity error in network environment

Systems and methods for analyzing data transferred through an SPI data bus are presented. In one exemplary preferred embodiment of the invention, an SPI data probe imitates an SPI device coupled to the SPI data bus and receives data from the SPI data bus so that the data may be analyzed. The SPI data probe transfers the data to an analysis unit without substantially altering impedance more than the SPI device would. The SPI data probe includes connectors configured for coupling the probe to the SPI data bus and for coupling the probe to an analysis unit. The SPI data probe also includes circuitry that may buffer, compensate and deskew the data as an SPI device would.

Systems and methods for analyzing data of an SPI data bus

Disclosed is a method for automatically testing the deskew setting for the clock in a parallel data interface. The deskew value is varied to a high and a low limit to the point where errors occur when transmissions occur. After determining the high and low operable limits of the deskew values, an optimum deskew setting may be determined and set for the system. The present invention may be used as a design verification technique, for optimizing a system after integration, or for further optimization of the deskew value after performing a training pattern for optimizing transmission performance.

Method for determining deskew margins in parallel interface receivers

A signal testing implementation provides significant advantages over conventional signal testing techniques. According to an exemplary embodiment, an apparatus for enabling signal testing such as SCSI signal testing in a test configuration includes a portable cable environment having a plurality of cables exhibiting a plurality of lengths and impedances. A user can selectively connect any one of the cables between a host device such as a server and a target device such as a disk subsystem. Signal measurement connectors which are connectable to the portable cable environment may be provided. According to an embodiment, each of the signal measurement connectors includes one or more test measurement points to enable collection of signal testing results.

Testing implementation for signal characterization

An improved PCI verification method and apparatus provides iterative testing of all desired conditions or protocol combinations in a PCI system. One or more commands may be tested in combination with one or more functional behavior parameters throughout a desired range of variable parameter values. In one aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in target operation is provided. In another aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in master operation is provided.

Growing community of inventors

Monument, CO, United States of America

William J Schmitz