International Business Machines Corporation

William J Nestork

Bernard S Meyerson

Ingrid E Magdo

Thomas Benjamin Faure

Steven Magdo

William E Dougherty, Jr

Stuart E Greer

Hans E Dietsch

William T Norris

Wilber D Pricer

John R Turnbull, Jr

Three-dimensional semiconductor structures are taught in which various device types are formed from a plurality of planar layers on a substrate. The major process steps include the formation of a plurality of alternating layers of material, including semiconductor and dielectric materials, forming a vertical access hole in the layers, processing the layers selectively to form active or passive semiconductor devices, and filling the access hole with a conductor. The ultimate structure includes a three-dimensional memory array in which entire dynamic memory cells are fabricated in a stacked vertical orientation above support circuitry formed on a planar surface.

Three-dimensional semiconductor structures formed from planar layers

A full wafer packing technique for semiconductor devices is provided. The semiconductor wafer is mounted on a substrate wherein the coefficient of thermal expansion of the substrate is matched to that of the wafer. The wafer is also provided with at least one bus member extending across the surface of the wafer to provide voltage power to the devices. Further, the packaging includes a cover, and a solid dielectric thermally conducting material which is disposed between and the wafer and substrate and fills the space between the cover and wafer and substrate.

Power distribution for full wafer package

A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by personalized surface wiring and preset substrate conductors.

Personalizable masterslice substrate for semiconductor chips

A process for forming complete dielectrically isolated monocrystalline silicon regions on a substrate by depositing a first epitaxial silicon layer embodying an N-type impurity on a low resistivity silicon substrate embodying a P-type impurity, forming annular P-type impurity regions in the first epitaxial layer, depositing the second epitaxial layer embodying an N-type impurity on the first epitaxial layer, forming annular P-type impurity regions in the second epitaxial layer in registry with the annular regions in the first epitaxial layer, converting the silicon substrate and the annular P-type regions in the first and second epitaxial layers into porous silicon material by an anodic treatment carried out in an aqueous solution of hydrofluoric acid, and oxidizing the porous silicon material to form silicon oxide. A semiconductor structure having a backing substrate of silicon oxide with monocrystalline silicon islands embedded therein. A preferred embodiment includes low resistivity regions that extend through the substrate.

Process for fabricating devices having dielectric isolation utilizing

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Hinesburg, VT, United States of America

William J Nestork