At&t Bell Laboratories

William J Nagy

Kuo-Hua Lee

Frederick Harrison Fischer

Janmye Sung

Nur Selamoglu

Thomas Evans Adams

James D Chlipala

Kuo H Lee

James N Billig

A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connection between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.

Method of fabricating an integrated circuit with lines of critical width

Integrated-circuit devices are provided with conductive paths or links which, by laser irradiation or electric current pulsing, can be severed or fused. In the interest of ease of fusing, preferred links have locally reduced thickness as achieved, e.g., by employing two steps of layer deposition and etching as follows: first, a layer of conductor material is deposited on a dielectric surface, and locally reduced in thickness by etching at one or several points selected for fusing, and, second, a further layer of conductor material is deposited, and then etched to produce a desired conductive path passing through such points.

Method of making severable conductive path in an integrated-circuit

A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connetion between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.

Integrated circuit

Severable conductive path in an integrated-circuit device

An integrated circuit includes a conductive fusible link (14) that may be blown by laser energy. The dielectric material (15) covering the fuse is etched away to expose the fuse. A protective dielectric layer (30) is formed on the fuse to a controlled thickness less than that of the interlevel dielectric. The resulting structure prevents shorts between conductors that might otherwise occur due to debris from the fuse-blowing operation, and provides protection to the integrated circuit. In addition, the fuse blowing operation is more consistent from fuse to fuse.

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Bethlehem, PA, United States of America

William J Nagy