Racal Data Communications Inc.

Racal-Milgo Limited

William J Miller

Chun C Lu

Ran F Chiu

Jay P Jayapalan

Jack E Stephenson

Richard B Joerger

Frank W Newdeck

Nick G Trbovich

A differential correlator for a receiver including a voltage controlled current source which is controlled by an input data signal which is based on a received signal. A switching circuit selectively couples the controlled current to one of two storage capacitors as a function of a reference signal. A comparison circuit compares the integrated voltages on the storage capacitors at the end of each integration period T to provide user data as a function of the comparison. A discharge circuit discharges the storage capacitors to a common initial voltage after the integrated voltages are compared.

Differential correlator circuit

A digital voice communication apparatus having improved echo suppression includes a transmission gain detection circuit for detecting a near talker signal and a receiver gain detection circuit for detecting a far talker signal. An echo detecting circuit detects which of the near talker and far talker signals has a lesser value and suppresses the gain of the one detected to have the lesser value. A far talker suppressing circuit detects whether the most recent peak gain in this near talker signal is greater than a threshold and is greater than the gain of the far talker signal. If this condition exists the far talker signal is suppressed. A near talker signal suppressing circuit detects whether the most recent gain of the far talker signal is greater than a threshold and is greater than the gain of the near talker signal. If so, the gain of the near talker signal is suppressed.

Digital voice transmission having improved echo suppression

A circuit arrangement is provided for switching serial data packets through a network destined for one of a plurality of possible outgoing lines. Minimal delay is achieved by shifting the data through a shift register having length equivalent to the destination address of the incoming serial data packet. The shift register addresses a memory which in turns controls a switch network so that the incoming packet is switched with minimal delay to an appropriate outbound line. By utilizing random access memory to translate from destination address to switch position, the system may be altered to correct for changes in the overall network caused by network failures or expansion network or to allow dynamic load balancing by directing data through the switch to a control computer which in turn rewrites the memory.

High speed packet switching arrangement

An apparatus for use in transmitting compressed digital voice data includes an analyzer for compressing digitized voice data according to an algorithm which produces a root mean square of the voice data. An analog to digital converter is used to convert analog voice signals to digital data as an input to the analyzer. An AGC circuit controls to analog voice signal to keep it within predetermined limits for digitization, with the AGC setting being determined by the root mean square of the digitized data. The digitized data includes data representative of the root mean square adjusted by the inverse of the change induced by the AGC. A speech synthesizer expands the digitized data at a remote location to convert it back to analog speech signals.

Digital voice compression having a digitally controlled AGC circuit and

A digital communication apparatus with improved echo suppression includes a circuit for detecting the gain of a far talker signal and a circuit for detecting the gain of a near talker signal. These gains are compared and echo suppression is accomplished by suppressing the lesser of the two gains.

A public-key data encryption system employing RSA public-key data encryption including a message encrypter capable of encrypting messages using a non-secret encryption key, a transmitter-receiver coupled to the message encrypter which transmits or receives an encrypted message to or from a remote location, the transmitter-receiver also being coupled to a decrypter capable of decrypting a received encrypted message using a decryption key which is a secret input to the decrypter, and an encryption-decryption key generator, including a microprocessor or other large-scale integrated circuit or circuits formed to generate a sequence of prime numbers beginning with a selected known prime number having a length relatively short with respect to the desired length of the last in the sequence of prime numbers, and which is constructed to form the sequence of prime numbers in the form hP+1 where P is the preceding prime number in the sequence, and to test hP+1 for primality by first determining if hP+1 has a GCD of 1 with x, wherein x is a composite number consisting of the product of all known prime numbers less than or equal to a pre-selected known prime number and if the GCD is not equal to 1, incrementing h to form a new hP+1 to be tested for a GCD equal to 1, and when a GCD is found to be 1, performing the primality tests to determine whether 2.sup.hP .ident.1 [mod (hP+1)] and 2.sup.h .notident.1 [mod (hP+1)], and if either 2.sup.hP .notident.1 [mod (hP+1)] or 2.sup.h .ident.1 [mod (hP+1)] further incrementing h and so on until a prime is found in this manner and then determining if the length of the prime number is of or greater than the desired length. If the hP+1 which has been determined to be prime is not of the desired length, hP+1 is placed in the sequence of prime numbers and a new h selected to be used to find the next prime number in the sequence in accordance with the above described procedure by forming a new hP+1 in which P is the previously determined prime number in the sequence of prime numbers. When a prime number in the sequence of prime numbers is found which is of the desired length it is input into the encryption-decryption key generator for generating the RSA public-key encryption and decryption keys.

RSA Public-key data encryption system having large random prime number

Communication over data links using binary synchronous protocol that is to be made secure according to the Federal data encryption standard (DES) is enhanced by utilizing an encrypted message format wherein the initialization vector for the DES algorithm is at the trailing end of the message. Additional information or control words may also be strung at the trailing end of the encrypted message format without causing throughput loss while enhancing the security and flexibility of the encrypted message in both point-to-point and multipoint systems.

Growing community of inventors

North Miami, FL, United States of America

William J Miller