Burr-brown Corporation

Burr-brown Research Corporation

William J Lillis

Jimmy R Naylor

Anthony D Wang

Stephen R Burnham

Robert L White

Justin A McEldowney

Adrian B Early

An electronically controllable low capacitance active bus line terminator achieves low output terminal capacitances by connecting emitters of switch transistors directly to the output terminals. Termination resistors are connected directly between an output of a voltage regulator circuit and collectors of the switch transistors. Emitters of optional clamp transistors can be connected to bases or collectors of the switch transistors to limit or prevent 'ringing' of bus conductors connected to the output terminals if the switch transistors are turned on. The bus conductors are thereby isolated from parasitic capacitances associated with the termination resistors and the collectors of the switch transistors when they are turned off.

Low capacitance electronically controlled active bus terminator circuit

A complementary current mirror includes a PNP transistor and an NPN transistor, one of which serves as a control transistor and the other of which serves as an output transistor. A V.sub.BE voltage generated by forcing a control current into or out of the emitter of the control transistor is imposed between the base and emitter of the output transistor to produce a controlled current in the collector of the output transistor. A first such current mirror, with an NPN control transistor, and a second such current mirror, with a PNP control transistor, are driven by the same control current to supply first and second input bias currents to a diamond follower circuit in the same integrated circuit as the first and second current mirror circuits to face the V.sub.BE voltage of the PNP and NPN transistors of the diamond follower circuit to be equal despite variation in saturation currents of the PNP and NPN transistsors. This results in zero input offset for the diamond follower circuit.

Complementary current mirror for correcting input offset voltage of

A subsurface zener diode is formed in an N.sup.- epitaxial region formed on a P type substrate. The N.sup.- epitaxial region is isolated by a P.sup.+ isolation region. An N.sup.+ buried layer region is disposed between a portion of the N.sup.- epitaxial region and the P type substrate. A first P.sup.+ region is formed in the middle of the N.sup.- epitaxial region at the same time as the P.sup.+ isolation regions. Second and third adjacent P.sup.+ regions also are formed in the N.sup.- epitaxial region adjacent to and slightly overlapping the first P.sup.+ region, all three P.sup.+ regions terminating at the N.sup.+ buried layer. An N.sup.+ region, formed during an emitter diffusion operation, has first and second opposed edges centered within the overlapping portions of the first, second, and third P.sup.+ regions. Two other opposed edges of the N.sup.+ region extend beyond the other edges of the first P.sup.+ region, forming N.sup.+ N.sup.- contacts to the N.sup.+ epitaxial region, enabling it to be reverse biased without an additional N.sup.+ contact region and a corresponding metal conductor. Masking alignment tolerances in the direction of the N.sup.+ N.sup.- overlap are eased, increasing overall processing yields.

Subsurface zener diode and method of making

A subsurface zener diode is formed in an N.sup.- epitaxial region formed on a P type substrate. The N.sup.- epitaxial region is isolated by a P.sup.+ isolation region. An N.sup.+ buried layer region is disposed between a portion of the N.sup.- epitaxial region and the P type substrate. A first P.sup.+ region is formed in the middle of the N.sup.- epitaxial region at the same time as the P.sup.+ isolation regions. Second and third adjacent P.sup.+ regions also are formed in the N.sup.- epitaxial region adjacent to and slightly overlapping the first P.sup.+ region, all three P.sup.+ regions terminating at the N.sup.+ buried layer. An N.sup.+ region, formed during an emitter diffusion operation, has first and second opposed edges centered within the overlapping portions of the first, second, and third P.sup.+ regions. Two other opposed edges of the N.sup.+ region extend beyond the other edges of the first P.sup.+ region, forming N.sup.+N.sup.- contacts to the N.sup.- epitaxial region, enabling it to be reverse biased without an additional N.sup.+ contact region and a corresponding metal conductor. Masking alignment tolerances in the direction of the N.sup.+ N.sup.- overlap are eased, increasing overall processing yields.

A digital audio system for high-fidelity replication of wideband audio material. The system comprises a high-speed, low-noise and low-distortion, digital-to-analog converter including means for reducing spurious switching currents in the reconstructed audio signal. Such a converter is employed in both the encoding and decoding portions of the system.

Analog to digital converter system for application to pulse code

A trimmable resistive scaling network suitable for use in digital-to-analog converters or the like. At least two trimmable resistors with low order integral relative values provide for either scaling up or scaling down with high accuracy.

Trimmable resistive scaling network suitable for digital to analog

A latch circuit utilizes a series-gated, emitter coupled logic structure including a current source providing a gate current substantially proportional to temperature for developing an output signal swing substantially proportional to temperature, thereby allowing the output signal swing to have a reduced magnitude at nominal temperatures. The load across which the output signal is developed includes a resistor coupled in series with a semiconductor P-N junction. Emitter areas of emitter-coupled transistor pairs within the latch circuit are mismatched for creating an offset tending to compensate changes in the voltage across the semiconductor junction within the load resulting from the switching action of the latch circuit. A bias circuit maintains the switching threshold reference voltage substantially intermediate the output signal swing. The semiconductor junction within the load of the latch circuit may correspond with the base-emitter junction of a transistor, and an additional load resistor may be coupled to the collector thereof for providing a second output signal swing of increased magnitude isolated from the feedback path of the latch circuit. In an alternate embodiment, the semiconductor junction within the load is eliminated, and a follower transistor is inserted within the feedback path of the latch circuit for level-shifting the output signal voltage developed across the load resistor and providing a low impedance source thereof.

Reduced swing latch circuit utilizing gate current proportional to

A digital-to-analog converter circuit includes an open-loop reference circuit for regulating a plurality of bit switch currents and utilizes a high-speed single-ended input interface network for level shifting digital input signals to the bit switches whereat the level shifted input signals switch against a substantially fixed threshold voltage. The single-ended input interface network includes a PNP input transistor coupled to an input terminal and coupled by a resistor to a regulated voltage. The PNP input transistor is coupled to a level shifting network including an emitter follower transistor and a zener junction biased by a current source. The threshold voltage is also developed by a level shifting network that includes a zener junction for compensating variations within the level shifting network of the single-ended input interface network.

Digital-to-analog converter having single-ended input interface circuit

An open-loop voltage reference circuit, adapted to regulate a plurality of bit switch currents within a digital-to-analog converter, includes a zener diode reference leg for developing a reference voltage. The reference leg also includes a base-emitter junction voltage multiplier for creating a compensating voltage having a temperature tracking coefficient that is equal and opposite to that of the zener diode junction voltage. The reference voltage developed by the reference leg is used to bias a temperature independent current within a slave leg, and a current mirror circuit mirrors the current within the slave leg for supplying a constant current to the reference leg. The magnitude of the reference voltage is reduced through a divider leg, and an emitter follower leg provides a low impedance bias voltage for driving the plurality of bit switch current sources. The open-loop voltage reference circuit is further adapted to compensate for second order errors caused by temperature induced variations in current gain and Early effect variations related to changes in the power supply voltage. A Gain Adjust feature is also provided for adjusting the bit switch currents without adversely affecting the regulation thereof.

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Tucson, AZ, United States of America

William J Lillis