Intel Corporation

William J Lambert

Krishna Bharath

Kaladhar Radhakrishnan

Zhichao Zhang

Sidharth Dalmia

Michael J Hill

Adel A Elsherbini

Mathew J Manusharow

Feras Eid

Omkar G Karhade

Zhenguo Jiang

Robert L Sankman

Sri Chaitra Jyotsna Chavali

Trang Thuy Thai

Beomseok Choi

Shawna M Liff

Sanka Ganesan

Mihir K Roy

Johanna M Swan

Yongki Min

Aleksandar Aleksov

Georgios C Dogiamis

Henning Braunisch

Nitin A Deshpande

Yikang Deng

Charles A Gealer

Huong T Do

Benjamin Jann

Jiwei Sun

Tyler N Osborn

Reynaldo Alberto Olmedo

Jonathan Jensen

Clive R Hendricks

Leigh E Wojewoda

Swathi Vijayakumar

Kirthika Nahalingam

Stephen Andrew Smith

Ozgur Inac

Venkat Anil K Magadala

Telesphor Kamgaing

Stephen L Morein

Debendra Mallik

Sasha N Oster

Kemal Aygun

John Stephen Guzek

Islam A Salama

Javier Soto Gonzalez

Brandon M Rawlings

Jonathan P Douglas

Suddhasattwa Nad

Sriram Srinivasan

Dong Zhong

Jimin Yao

Christopher Schaef

Alexander Slepoy

Xiaoqian Li

Daniel N Sobieski

Christopher J Nelson

Meizi Jiao

Srikrishnan Venkataraman

Anne Augustine

Hector A Aguirre Diaz

Patrick R Morrow

Qing Ma

Chia-Pin Chiu

Paul B Fischer

Gerald S Pasdast

Amruthavalli Pallavi Alur

Harish Krishnamurthy

Mitul Bharat Modi

Xavier Francois Brun

Sergio Antonio Chan Arguedas

Thomas John Fitzgerald

Gregorio R Murtagian

Bharat P Penmecha

Sri Chaitra J Chavali

Aravindha Antoniswamy

Shamala Chickamenahalli

Shrenik Kothari

Rajapandian Ayyanar

Kedar Dhane

Haifa Hariri

Siddharth Kulasekaran

Nicolas Butzen

Sri Chaitra Chavali

Sathya Narasimman Tiagaraj

Divya Mani

Ahmed Abou-Alfotouh

Punita Sullhan

Martin Rodriguez

Vivek Kumar Rajan

Timothy Francis Schmidt

Anuj Modi

Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

Power delivery through capacitor-dies in a multi-layered microelectronic assembly

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.

Microelectronic assemblies with direct attach to circuit boards

A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

Packaging architecture for disaggregated integrated voltage regulators

In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

Conformal power delivery structure for direct chip attach architectures

Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.

Antenna modules and communication devices

In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

Integrating voltage regulators and passive circuit elements with top side power planes in stacked die architectures

Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.

Magnetic core inductors in interposer

Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.

Radio frequency front-end structures

An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.

High-throughput additively manufactured power delivery vias and traces

Embodiments disclosed herein include power transformers for microelectronic devices. In an embodiment, a power transformer comprises a magnetic core that is a closed loop with an inner dimension and an outer dimension, and a primary winding around the magnetic core. In an embodiment, the primary winding has a first number of first turns connected in series around the magnetic core. In an embodiment, a secondary winding is around the magnetic core, and the secondary winding has a second number of second turns around the magnetic core. In an embodiment, individual ones of the second turns comprise a plurality of secondary segments connected in parallel.

Package embedded magnetic power transformers for SMPS

Embodiments include inductors and methods to form the inductors. An inductor includes a substrate layer that surrounds a magnetic layer, where the magnetic layer is embedded between the substrate layer. The inductor also includes a dielectric layer that surrounds the substrate and magnetic layers, where the dielectric layer fully embeds the substrate and magnetic layers. The inductor further includes a first conductive layer over the dielectric layer, a second conductive layer below the dielectric layer, and a plurality of plated-through-hole (PTH) vias in the dielectric and substrate layers. The PTH vias vertically extend from the first conductive layer to the second conductive layer, and the magnetic layer in between the PTH vias. The magnetic layer may have a thickness that is substantially equal to a thickness of the substrate layer, where the thickness of the magnetic layer is less than a thickness defined between the first and second conductive layers.

Package embedded magnetic inductor structures and manufacturing techniques for 5-50 MHZ SMPS operations

An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

Power delivery structures

Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

Multi-phase switching regulators with hybrid inductors and per phase frequency control

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

High performance integrated RF passives using dual lithography process

Growing community of inventors

Tempe, AZ, United States of America

William J Lambert