Ncr Corporation

William J Kass

Michael R Hilley

Lee W Hoevel

A split-range address detector and translator for interfacing a system processor with a memory array. The split-range detector generates a select signal for the memory array whenever an input address received from the system processor resides in either of two, non-contiguous, address ranges. The split-range detector includes a first range detector which generates a first range detection signal when the address received from the system processor is within a first, lower, range of addresses, and a second range detector which generates a second range detection signal when the input address is within a second, upper, range of addresses. The output signals are combined together to produce the select signal for the memory array. The address ranges are defined by upper and lower address limits stored within programmable registers. The address translator includes subtraction logic which determines the size of the address gap between the two address ranges from the stored address limits and generates a translated address by subtracting the size of the address gap from the input address. A bus multiplexer responsive to the second range detection signal provides the input address information to the memory array when the input address is within the lower address range and provides the translated address to the memory array when the input address is within the upper range of addresses. Thus, addresses received from the system processor are mapped into a single contiguous address space within the memory array.

Memory range detector and translator

A method for controlling access to a memory includes the step of defining a group of priority codes, each of which represents an order for granting simultaneous memory access requests. One of the group of priority codes is selectively provided to a memory controller. A request to access memory is then granted according to the selected priority code.

Method for prioritizing memory access requests using a selected priority

A computer system is provided including a main memory prefetch cache which enhances the retrieval of instructions (code and data) stored in the main memory of a computer. The computer system includes a processor and a processor cache coupled thereto. A memory controller is coupled to the processor and includes a main memory prefetch cache. The memory controller also includes control circuitry which determines if a current line requested by the processor is stored in the prefetch cache, and if so, the memory controller retrieves the current line from the prefetch cache and provides the current line to the processor. The next line is then retrieved from the main memory and is overwritten over the current line in the prefetch cache. Otherwise, if the memory controller determines that the prefetch cache does not contain the current line requested by the processor, then the current line is retrieved from the main memory and is provided to the processor. The next line is then retrieved from the main memory and is stored in the prefetch cache at a register location which was occupied by the least recently used line in the cache. The invention includes circuitry and methodology for determining the least recently used line stored within the prefetch cache.

Computer apparatus including a main memory prefetch cache and method of

In computers, a test of memory is generally performed at the time of powering up. In one form of the invention, this type of test is run on part of Random Access Memory (RAM), while allowing data or a program to reside in another part. Then, after the partial test is completed, the data is transferred into the RAM just tested, and the RAM which previously held the data is tested. Thus, the data can co-exist in memory while the test runs, by being shuttled from one location to another.

Non-destructive memory testing in computers

A method and system of maintaining coherency for a data block transferred from a main memory to a cache memory. The data transfer is recorded in a tag register in the main memory. An overwrite of the data block is detected by comparing main memory data writes with the recorded transfer. The cache memory is only notified in the event an overwrite is detected. An invalid flag is then set in the cache.

Method and system for maintaining data coherency between main and cache

A system and method for requesting access to refresh a computer memory. Two lines are connected between a timer and arbiter. A memory refresh request signal is provided on the first line and is accorded a relatively low priority by the arbiter. If the first request is not granted within a predetermined period of time, a second memory refresh request signal is provided on the second line and is accorded a relatively high priority by the arbiter.

System and method for requesting access to a computer memory for

A system comprising a memory for transferring m data bytes at a time, first and second busses each having a width of less than m data bytes, first parallel m byte wide read and write registers connected between the first bus and the memory and second parallel m byte wide read and write registers connected between the second bus and the memory.

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Easley, SC, United States of America

William J Kass