Raytheon Company

Santa Barbara Research Center

He Holdings, Inc.

William J Hamilton, Jr

Eli E Gordon

Ronald W Berry

David R Rhiger

Michael S Ray

Paul R Norton

William L Ahlgren

Christopher L Fletcher

Scott M Johnson

Sanghamitra Sen

A hybrid microelectronic array structure is fabricated from a readout integrated circuit array of microelectronic integrated circuits and a supported array of supported islands. The supported islands include one or more supported elements, with a respective supported element for each of the readout integrated circuits. The supported array is made by depositing the first semiconductor region onto a supported substrate and depositing the second semiconductor region onto the first semiconductor region, and defining supported islands as electrically isolated segments. On each supported element, a first interconnect is formed to the first semiconductor region and a second interconnect is formed to the second semiconductor region. The supported array is joined to the readout integrated circuit array by an interconnect structure, preferably a bump interconnect structure, to form the hybrid microelectronic array structure, with each readout integrated electrically interconnected to the respective one of the supported elements.

Hybrid microelectronic array structure having electrically isolated supported islands, and its fabrication

An integrated optical device array structure has a plurality of interconnected solid state microelectronic optical device elements associated together on a substrate structure. The optical device elements may be optical detectors or optical emitters. Each optical device element lies on a nonplanar optical array surface. Each optical device element includes an opto-electronic device that interconverts an optical signal and an opto-electronic device electrical signal, and an electrical interface circuit that is in electrical communication with the opto-electronic device electrical signal. The optical device array structure may be fabricated by preparing a flat array of optical device elements and deforming the flat array into the required shape.

Nonplanar integrated optical device array structure and a method for its fabrication

A monolithic microelectronic array structure includes a microelectronic integrated circuit array having a first plurality of microelectronic integrated circuit elements each deposited on a front side of a substrate. The substrates are physically discontinuous so that each substrate comprises a substrate island which is physically separated from the other substrate islands. The monolithic microelectronic array structure optionally includes a first plurality of input/output elements with a respective input/output element associated with and directly connected to each of the microelectronic integrated circuit elements, and a second plurality of electrically conductive interconnects extending between the microelectronic integrated circuit elements of adjacent substrate islands. The monolithic microelectronic array structure may be planar, or it may be curved.

Monolithic microelectronic array structure having substrate islands and its fabrication

A large area radiation detector (1) includes a volume of semiconductor material (24) that is responsive to ionizing radiation for generating charge carriers, a first electrode (26) coupled to one surface of the volume of semiconductor material, and a plurality of second electrodes (20, 22) coupled to a second surface of the volume of semiconductor material. Individual ones of the second electrodes are associated with an underlying region of the volume of semiconductor material for collecting charge carriers from the underlying region. The detector further includes circuitry (30, 31, 32) coupled to the plurality of second electrodes for summing charge carriers collected by the plurality of second electrodes to produce an output signal, and a mechanism for selectively decoupling individual ones of the second electrodes from the circuitry. In one embodiment the circuitry includes electrically conductive traces (16) that couple individual ones of the second electrodes to a summing junction (31), and the mechanism for selectively decoupling includes physically opening a trace to disconnect the second electrode from the summing junction. In a further embodiment the mechanism for selectively decoupling includes a semiconductor switch (34) that is coupled in series with each of the traces.

Method for yield and performance improvement of large area radiation

A three terminal solid-state ionizing radiation detector (10) includes a first layer (18) of a substantially intrinsic Group II-VI compound semiconductor material, such as CdZnTe. The first layer is responsive to incident ionizing radiation for generating electron-hole pairs. The detector further includes a second layer (24) of Group II-VI compound semiconductor material and a third layer (20) of Group II-VI compound semiconductor material that is interposed between first surfaces of the first layer and the second layer. The third layer functions as a grid layer. A first electrical contact (12, 17) is coupled to a second surface of the first layer, a second electrical contact (29, 30) is coupled to a second surface of the second layer, and a third electrical contact (22) is coupled to the third layer for connecting the detector to an external circuit that establishes an electric field across the detector. The electric field causes holes to drift away from the grid layer towards the first contact while electrons drift towards and through the grid layer, through the second layer, and towards the second contact for generating a detectable output signal pulse. Because of the presence of the grid layer only the electrons contribute to the output pulse. The grid layer has a conductivity type such that electrons are a minority charge carrier within the grid layer.

Single carrier-type solid-state radiation detector device

Gamma ray detectors (20, 130) are provided with a detector layer (30) that is formed of Hg.sub.x Cd.sub.1-x-y Zn.sub.y Te, wherein 0&lt;x&lt;0.05 and 0.ltoreq.y&lt;0.5. The Hg percentage in the group II sublattice of this detector layer is limited to replace Cd vacancies. These Cd vacancies are native point defects which degrade the resolution of gamma ray detectors because they facilitate early electron-hole recombination and time delays of current carriers.

Gamma ray detector with improved resolution and method of fabrication

A layer (32) of a HgCdTe compound epitaxially contacts a buffer structure, which in turn epitaxially contacts a silicon substrate (22). The buffer structure is formed of II-VI compounds, and preferably includes at least one layer (24) of a ZnSeTe compound epitaxially contacting the silicon substrate (22) and a layer (30) of a CdZnTe compound overlying the ZnSeTe compound layer (24). The ZnSeTe compound layer (24) may be provided as a single graded layer having a composition of ZnSe adjacent to the silicon and a composition of ZnTe remote from the silicon, or as two distinct sublayers with a ZnSe sublayer (26) adjacent to the silicon substrate (22) and a ZnTe sublayer (28) remote from the silicon substrate (22).

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Ventura, CA, United States of America

William J Hamilton, Jr