Motorola Corporation

Advanced Micro Devices Corporation

Si Diamond Technology, Inc.

California Micro Devices Corp.

William J Donoghue

Glenn E Noufer

Stephen H Kelley

Claude Hilbert

Rodney C Tesch

Chadwick N Marak

Robert C Baker

A regulator circuit for use with integrated circuits protects downstream devices from the application of unregulated voltages during start-up or other initialization. The circuit includes an op amp which controls a regulator during steady state operation, and also includes a switching portion which responds to a reset signal and disconnects the op amp from the voltage regulator to prevent unregulated voltages from reaching the output node during start-up. During start-up, a current mirror is used to supply an initial voltage reference to the op amp, and upon establishment of steady state operation, the regulator turns off the current mirror and reconnects the op amp to the voltage regulator to allow the op amp and voltage regulator to control the output node.

System and method for startup bootstrap for internal regulators

A system and method for producing uniform energy dissipation in display pixels with widely varying electrical characteristics in order to equalize light output and improve yield within a matrix addressable display panel. The present invention is implemented within a driver circuit utilizing the concept of current integration. A reference voltage, which is proportional to the most efficient pixel within the display is compared to the energy dissipated within a particular pixel during illumination of that pixel. A current mirror circuit supplies a current equivalent to the current provided to the object pixel to an integrator circuit resulting in a rising voltage within the integrator circuit. The rising voltage is proportional to the energy being dissipated within the current pixel. Once the rising voltage is equal to or greater than the reference voltage, current is removed from the object pixel.

System and method for achieving uniform screen brightness within a matrix display

A sense amplifier detecting a small current differential between a selected memory cell and a reference cell in a memory array includes a first pass transistor, a second pass transistor, a cross-coupled transistor arrangement and a differential amplifier. The cross-coupled transistor arrangement detect a small current differential between a bit sense current line and a bit sense reference current line. The difference current is amplified by the differential amplifier to produce an output data voltage indicative of the binary state of the selected memory cell.

High gain sense amplifier for small current differential

A memory which has memory cells with first and second orientations also has reference cells with first and second orientations. When a memory cell with the first orientation is selected, an output of a reference cell with the first orientation is compared to that of the selected cell with the first orientation. When a memory cell with the second orientation is selected, an output of a reference cell with the second orientation is compared to that of the selected cell with the second orientation.

Orientation of reference cells in a memory

A non-volatile memory has a plurality of coupling transistors for coupling bit lines to an equalization line in response to an equalization pulse. The equalization line has capacitance as do the bit lines. Prior to the occurrence of the equalization pulse, the unselected bit lines are charged to a first predetermined voltage, and the equalization line is charged to a second predetermined voltage by a high impedance reference voltage generator. A pulse generator provides the equalization pulse in response to an address transition.

Circuit for equalizing bit lines in a ROM

A circuit uses a pair of transistors in series to provide an output pulse which indicates an address transition has occurred. A duration of joint conductivity of the pair of transistors determines the duration of the output pulse. For an address transition, one of the transistors is rapidly turned on while the other is slowly turned off with a slow fall time. The fall time is adjustable to achieve an adjustable duration of joint conductivity, and thereby an adjustable output pulse width.

Circuit for address transition detection

A virtual ground memory which has four state cells coupled to bit lines has a load directly connected to each bit line to reduce the degradation of the output of a selected memory cell due to voltage drop caused by current flow between load and selected memory cell. Additionally, loads which are coupled to the bit lines are also coupled to an adjacent virtual ground line to avoid providing a separate power supply line for the loads.

Circuit for reducing degradation of voltage differential in a memory

A TTL to CMOS input buffer accomplishes buffering a TTL signal to a CMOS signal without static current flow when the TTL is a logic '1' by isolating the input from an input P channel transistor and using feedback from an input N channel transistor to turn off the P channel transistor. A second P channel transistor is used to couple a positive power supply voltage to the input P channel transistor in response to an output from the N channel transistor.

TTL to CMOS input buffer

A TTL to CMOS input buffer accomplishes buffering a TTL signal to a CMOS signal without requiring current flow through a CMOS input inverter in a static condition by introducing a reference voltage to match the lowest level of a logic '1' of the TTL signal. The input inverter has a P channel transistor which, by having a source at the reference voltage, does not turn on when the TTL signal is at the lowest level of a logic '1'. The reference voltage is selected to be less than the lowest level of a logic '1' minus the threshold voltage of the P channel transistor.

TTL to CMOS Input buffer

A pull-up circuit for a memory provides an additional natural transistor between a power supply and diode-connected transistors which reduces the voltage on bit sense lines sufficiently to allow selected column select transistors to turn on prior to a memory cell being enabled. Additional control circuitry further reduces the voltage to the diode-connected transistors when no memory cells have been selected to be enabled to compensate for the reduction in voltage drop across the natural transistor when no current is flowing through it.

Pull-up circuit for a memory

A memory array having improved isolation between the bit sense common lines is provided by using diode connected transistors. The diode connected transistors substantially eliminate any current flow between bit sense common lines when a certain portion of the column select circuitry has not been selected. Since the blocking transistors prevent current flow there is no noise generated to be coupled to one of the control lines. This results in a memory array which can operate at higher speeds since better differential signals are established to be sensed by the sense amplifier.

Growing community of inventors

Round Rock, TX, United States of America

William J Donoghue