At&t Bell Laboratories

William J Dally

Prathima Agrawal

Anjur S Krishnakumar

An arrangement for implementing graph operations, generally, and circuit simulations in particular employing a plurality of substantially identical high speed special purpose processing elements (PE) that are flexibly interconnected through a switch to form a cluster. In addition to the processing element (PE) being programmable, the interconnection switch permits dynamically altered routing of signals between the processing elements. The processing elements include a queue unit which permits high speed asynchronous communication between the elements. Additional advantage is attained with a hierarchical arrangement where a plurality of clusters are interconnected in an n-cube arrangement, and all of the clusters communicate with a host computer.

Growing community of inventors

Middlesex County, MA, United States of America

William J Dally