Texas Instruments Corporation

Iowa State University Research Foundation Inc

William J Bright

Martin Kithinji Kinyua

Marco Corsi

Visvesvaraya Appala Pentakota

Shagun Dusad

Richard K Hester

Mark B Weaver

Jiankun Hu

Robert Floyd Payne

Michael Oliver Polley

Ranjit Gharpurey

Hasibur Rahman

Yang Xu

William David Smith

A circuit having an input and an output, the circuit comprising: a first amplifier having a first input, a second input and an output coupled to the output of the circuit; a first capacitor having a first terminal coupled to the first input of the first amplifier and a second terminal coupled to the output of the first amplifier; a first resistor having a first terminal coupled to the first input of the first amplifier and a second terminal; a buffer having an output coupled to the second terminal of the first resistor and an input; a second resistor having a first terminal coupled to the output of the first amplifier and a second terminal coupled to the input of the buffer; a second capacitor coupled between the input of the buffer and ground; and a third resistor coupled between the input of the buffer and the input of the circuit.

Multiple feedback filter

A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.

Counter-based SYSREF implementation

Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sampling rate) with low power consumption. This is accomplished through the use of multiplexed, front-end track-and-hold (T/H) circuits that sample on non-overlapping portions of a clocking signal in conjunction with 're-used' or shared analog processing circuitry.

Power and area efficient interleaved ADC

System and method for improved time-interleaved analog-to-digital converter arrays which reduces sampling mismatch distortion found in prior art arrays. There may be two causes of non-uniform sampling mismatch in a TI-ADC array, a mismatch due to skew and a mismatch due to clock jitter. To minimize non-uniform sampling mismatch, the mismatch due to skew can be addressed. A preferred embodiment comprises adjusting a delay imparted on the sampling clock by an adjustable delay in each channel of a plurality of channels in the TI-ADC array to minimize skew and randomly switching between two delays that span a zero-skew delay to reduce residual skew in each channel and thus eliminate (or reduce) frequency domain tones caused by non-uniform sampling mismatch.

System and method for improved time-interleaved analog-to-digital converter arrays

An analog-to-digital converter apparatus has a plurality of stages. Each stage includes a residue amplifier having a first and second amplifier unit. Each of the amplifier units has a first input locus, a second input locus and an output locus. The amplifier units cooperate in receiving a differential input data signal at the first input loci. A DC level setting signal unit is coupled with the second input loci and provides a DC level setting current in a first current direction. A counter-current signal generating unit is coupled with the second input loci via a single coupling locus common with the second input loci and provides a control current signal to the second input loci in a second current direction opposite to the first current direction. The control current signal provides a DC level control for each of the amplifier units.

Method and apparatus for reducing noise in analog-to-digital converter devices

A circuit and method that provides a cascode current source/sink with high output impedance. In one example, the dependency on the external load is reduced by directing a compensation current corresponding to change in base current in the cascode (Q) in an approach such that the compensation current cancels out the error of the cascode (Q). In a further example, biasing circuitry () is included and arranged such that change in base current of the cascode (Q) is detected and a corresponding current is summed at the emitter of the cascode (Q) such that the collector current of the cascode (Q) remains unchanged.

Current source/sink with high output impedance using bipolar transistors

Echo cancellation in data communication between modems utilizes analog echo cancellation to lessen reduction of usable dynamic range of the received signal at the input to the analog-to-digital converter (DAC) in the receiver. Two digital-to analog (D/A) conversions are provided in the modem's analog front end (AFE). One generates the analog signal for transmission. The other generates an analog representation of a cancellation signal that is used to electronically cancel the echo before analog-to-digital (A/D) conversion of the received signal. A preferred embodiment utilizes multiplexed DAC architecture to emulate two DACs by sharing DAC circuitry between data paths of the two D/A conversions.

DAC architecture for analog echo cancellation

A buffer circuit includes a differential pair output switch having an additional NPN device and resistor operational to increase the common mode output voltage of the buffer during a switching event, such that the voltage movement at the common emitter node of the differential pair output switch for the buffer circuit is decreased to substantially reduce distortion of an output signal associated with a DAC that employs the buffer circuit.

Differential pair with high output signal crossover

A current correction circuit eliminates beta mismatches between a thermometer encoded segment and a R-2R ladder segment of a current steering digital-to-analog converter The circuit consists of three replica MSB unit current sources, I , I and I . The replica current I acts as a replica to a cascode device of the MSB unit of the current steering DAC The replica current I replicates an effective base current equal to the total base current in the R-2R ladder circuit portion of the current steering DAC The replica current I replicates the total base current of the L output switches in the LSB segment of the current steering DAC A high impedance summing node produces a correction current I &equals;I &minus;(I &plus;I ). This current is equal to the current difference between an MSB unit and the LSB segment This correction current is then subtracted from the MSB unit current source that supplies current into the R-2R ladder such that the current supplied to the R-2R ladder will be equal to the MSB replica current source minus the correction current.

Correction circuit for beta mismatch between thermometer encoded and R-2R ladder segments of a current steering DAC

This document describes a simple modification to the traditional pipelined analog-to-digital converter (ADC) architecture that reduces the signal swing of the inter-stage amplifier by a factor of two. This is a significant advantage when low power supply voltages limit the output range of operational amplifies. The modification requires no additional hardware and produces no additional power consumption.

Pipelined analog-to-digital converter with relaxed inter-stage amplifier requirements

A pipeline analog-to-digital conversion system (,) includes a plurality of cascaded subconverter stages (,) and a digital correction unit (,). Each subconverter stage (,) includes an n-bit analog-to-digital converter (,), an n-bit digital-to-analog converter (,), and an arithmetic unit (,). The n-bit analog-to-digital converter (,) generates a second intermediate digital signal (,) as a function of a first input analog signal (,) and a corresponding first intermediate digital signal (,) received from a previous stage (,).

Pipeline analog-to-digital conversion system using a modified coding scheme and method of operation

A pipeline analog-to-digital conversion system (10) includes a plurality of cascaded subconverter stages (12) and a digital correction unit (18). Each subconverter stage (12) includes an n-bit analog-to-digital converter (36), an n-bit digital-to-analog converter (38), and an arithmetic unit (42). Arithmetic unit (42) simultaneously samples a second input analog signal (34) and produces an output analog signal (44) representative of the difference between a first input analog signal (32) and a corresponding intermediate analog signal (40).

Pipeline analog-to-digital conversion system using double sampling and

Methods and apparatus for an analog-to-digital converter (ADC) with reduced comparator-hysteresis effects. One embodiment uses a charge-redistribution ADC. One method performs an initial coarse analog-to-digital conversion to avoid overdriving an analog voltage comparator. One such method includes a redundant capacitor in an array of charge-redistribution capacitors used in the ADC for sample-and-hold and successive-approximation functions. Another method performs a traditional initial successive-approximation analog-to-digital conversion, and then performs an additional conversion-step test based on the least-significant bit of the initial result to correct for comparator errors in the initial conversion.

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Dallas, TX, United States of America

William J Bright