Other

Crosspoint Solutions, LLC

Ocz Technology Group, Inc.

Novasolix, Inc.

Toshiba Corporation

Oc2 Technology Group, Inc.

William J Allen

Christopher E Phillips

Laurence H Cooke

Laurence Hager Cooke

Franz Michael Schuette

Karl Reinke

Dokyun Kim

Leon A Chavis

A solar antenna array may comprise an emitter that may convert visible light into black body infrared radiation, and an array of antennas that may capture and convert the black body radiation into electrical power. Methods for constructing the solar antenna array may include using thermal insulation, high-gain low-e glass, and gasses with minimal heat transfer. A black body infrared antenna array may augment the electrical power from a visible light antenna array by converting its waste heat into additional electrical power.

Black body infrared antenna array

A solar antenna array may comprise an array of randomly placed carbon nanotube antennas that may capture and convert sunlight into electrical power. Methods for constructing the solar antenna array may use a mold and self aligning processing steps to minimize cost. Designs may be optimized for capturing a broad spectrum of non-polarized light. Alternatively, the array may generate light, and when connected in to an array of independently controllable sections may operate as either a reflective or light transmitting display.

Solar antenna array and its fabrication and uses

A PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system. The interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the interface card, an interface port configured to mate with a connector of the cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the expansion slot and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard. The interface card and cable lacks the capability of transmitting power therethrough to a PCIe-compliant peripheral device connected to the interface card through the interface port.

Method of connecting a PCIe bus extension system

PCIe bus extension system, method and interfaces therefor

A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping.

Method and apparatus for reducing write cycles in NAND-based flash memory devices

A solid-state mass storage device and method for its operation that includes performing preemptive scrubbing of data during offline periods or disconnects from a host system to which the mass storage device is attached. The device includes a system interface adapted to connect the drive to a host system, at least one nonvolatile memory device, controller means through which data pass when being written to and read from the memory device, a volatile memory cache, a system logic device, and an integrated power source for powering the drive. The system logic device is configured to operate when the drive is not functionally connected to a host system, execute copy commands without accessing a host system, and prioritize preemptive scrubbing of addresses in the memory device on the basis of risk of data loss based on one or more parameters logged by the internal system logic device.

Mass storage device and method for offline background scrubbing of solid-state memory devices

Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge connector, a memory component, and first and second voltage planes adapted to supply the core supply voltage and the input/output supply voltage to the memory component. The first voltage plane receives a system input voltage from the edge connector, and the second voltage plane is connected to the first voltage plane to receive a second voltage that is either higher or lower than the system input voltage. One of the first and second voltage planes is connected to the memory component to supply the core supply voltage thereto, and the other voltage plane supplies the input/output supply voltage to the memory component.

Memory modules and methods for modifying memory subsystem performance

A field programmable gate array integrated circuit which has numerous features for testing prior to programming the antifuses in the integrated circuit is provided. The circuits used to program the antifuses are also used for much of the preprogramming testing. The functionality of continuous series transistors and latch logic blocks may be tested together with the continuity of their programmable connections. Programmable input/output buffer circuits and clock circuits which set the desired clock network paths may be tested with signals on a serial scan path which passes through the input/output buffer circuits and clock circuits. Process characterization tests without the requirement of high-speed test equipment are also provided.

Preprogramming testing in a field programmable gate array

A method for programming antifuses is described. Programming current pulses are driven through a selected antifuse. The resistance through the antifuse is then measured and compared to a predetermined resistance value. These measuring, comparing and driving steps are repeated until the measured resistance is less than a predetermined resistance value and the antifuse is annealed by driving a predetermined amount of current through the antifuse for a first predetermined amount of time and ramping down the current in a predetermined manner in a second predetermined amount of time. With this programming method no complex methods and circuits to reverse the polarities of voltage across and currents through the antifuse are required.

Method for programming antifuses for reliable programmed links

An alarm apparatus for detecting the removal of a handgun from a plate where the handgun is kept for quick accessibility. Embedded sensors detect the force exerted by the handgun on the plate. A handgun is placed on the plate and upper and lower threshold controls are adjusted to create a window encompassing the force exerted by the handgun. An alarm sounds if the force on the plate exceeds the window.

Alarm apparatus for handgun security

An adjustable movable guard mechanism for a saw bar of a chain saw over which an endless chain travels which guard mechanism having a first part which covers at least a part of the forward end of the contoured plate and a second part which forms a ski for guiding the chain saw along a surface to be cut.

Growing community of inventors

Cupertino, CA, United States of America

William J Allen