International Business Machines Corporation

William Infantolino

Sanjeev Balwant Sathe

David V Caletka

Voya Rista Markovich

George Henry Thiel

William Louis Brodsky

Eric A Johnson

Li Li

Krishna Darbha

Steven G Rosser

David James Alcoe

Virendra R Jadhav

An electronic package, such as a chip carrier, with an optimized circuit pattern having a circuitized substrate with a first and second circuit pattern is provided. The circuitized substrate includes a corner surface region. The second circuit pattern is electrically connected to the first circuit pattern on the corner surface region of the circuitized substrate and is positioned in such a manner so as to substantially inhibit cracking of the first circuit pattern during flexure of the chip carrier.

Electronic package with optimized circuitization pattern

An electronic packaging structure and method of forming thereof wherein the structure is constituted of a modular arrangement which reduces stresses generated in a chip, underfill, and ball grid array connection with a flexible substrate in the form of an organic material, which stresses may result in potential delamination due to thermally-induced warpage between the components of the modular arrangement.

Method and packaging structure for optimizing warpage of flip chip organic packages

A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.

Wafer with semiconductor chips mounted thereon

A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.

Land grid array stiffener for use with flexible chip carriers

Semiconductor chip module and method of manufacture of same

Land grid array stiffener use with flexible chip carriers

A ribbon cable includes electrical conductors surrounded by an insulator and vent tubes positioned adjacent and parallel to the conductors and insulator. The vent tubes allow airflow between an internal area of the enclosure and an external atmosphere and prevent access to the internal area of the enclosure.

Dual purpose ribbon cable

A test structure tests an electronic card having electrical contacts on one face and a chip on the other face. By way of example, the electrical contacts on the card comprise an array of solder balls. The structure comprises a socket for receiving the card such that the electrical contacts of the card face electrical contacts within the socket. The structure further comprises a plate, received over the socket and having at least two ribs which protrude downwardly from one face of the plate and are positioned over the socket to engage a center portion of the chip when the card is received in the socket. The plate also has at least two holes. One of the ribs is positioned between the two holes but does not surround either of the holes. Consequently, forced air can flow downwardly through the holes in the plate, horizontally between the plate and the chip and out of the test structure. Preferably, the two ribs cross each other, and there are four holes in the plate which are arranged in four respective quadrants defined by the cross.

Growing community of inventors

Vestal, NY, United States of America

William Infantolino