Analog Devices,inc.

Analog Devices Global

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Active Mind Technology R&d Limited

William Hunt

Michael F Keaveney

Eamon Hynes

John O'Dowd

Patrick G Crowley

Colin Gerard Lyden

Christopher Peter Hurrell

Oliver J Kierse

Philip Eugene Quinlan

John M Wynne

Kenneth J Mulvaney

Thomas J Conway

John W McGuire

Patrick J Meehan

Donal G O'Sullivan

Michael Hennessy

Peter G Meehan

Padraic Moran

Mark T Kelly

John R Martin

Padraig Fitzgerald

Damien Joseph McCartney

Denis Ellis

Arindam Raychaudhuri

Michael G Tuthill

Kaushal Kumar Ja

Michael T Tuthill

David A Phelan

A system for data collection during a game includes a positioning system for determining various locations of a user during the game, a tag reader for reading a passive RFID tag held in close proximity to the tag reader, and a processor for correlating the location of the user with the time at which a tag is read to enable action locations for the game to be determined.

Data collection during a game

A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.

Method of improving noise immunity in a signal processing apparatus, and a signal processing apparatus having improved noise immunity

A system for golf data collection comprises an apparatus arranged to be worn about the body of a golfer during a game of golf. The apparatus includes a positioning system for determining various locations of a golfer during the game, a tag reader for reading a club held in close proximity to the apparatus around the time of striking a golf ball, and a processor for correlating the location of the golfer with the time at which a tag is read to enable the path of a golf ball throughout the game of golf to be determined.

Golf data collection

Disclosed are a method, device, and system for a microelectromechanical (MEM) device control system that can control the operation of a MEM device. The system can include a microelectromechanical device and a control circuit. The micromechanical device can include a moveable member coupled to an electrical terminal, a sensor, responsive to a movement of the moveable member, can output a sensor signal based on the movement of the moveable member, and an actuating electrode for receiving a control signal. The control circuit can be responsive to the signals output by the sensor and outputs the control signal to the actuating electrode.

Control techniques for electrostatic microelectromechanical (MEM) structure

A sealed capacitive sensor includes a substrate having a diaphragm forming a first plate of a capacitor; a second fixed plate of the capacitor spaced from the diaphragm and defining a predetermined dielectric gap and a sealing medium connecting together the substrate and fixed plate in an integrated structure and hermetically sealing the gap.

Sealed capacitive sensor

A spaced, bumped component structure including a first plate, a second plate spaced from the first plate by a first gap, a plurality of solder bumps interconnecting the plates and defining the first gap; at least one of the plates having an anomalous section including one of a raised platform and recess for defining a second gap having a different size from the first gap.

Spaced, bumped component structure

An FSK demodulator system with tunable spectral shaping including a pair of quadri-correlators responsive to first and second quadrature signals, one of the pair deriving first and second signals representative of the frequency deviation of the quadrature signals at even integer multiples of the frequency deviation and for resolving the modulated FSK data represented by the quadrature signals and the other of the pair deriving first and second signals representative of the frequency deviation of the quadrature signals at odd integer multiples of the deviation frequency and for resolving the modulated FSK data represented by the quadrature signals, and a delay control circuit for setting a delay to each of the pair of quadri-correlators to control the first and second signals representative of the frequency deviation of the quadrature signals derived by each of the pair of quadri-correlators and generate a tuned spectral response at both even and odd integer multiples of the frequency deviation.

FSK demodulator system and method

A capacitive sensor including a housing having a hermetically sealed cavity, a plate in the cavity, a diaphragm forming a part of the cavity and spaced from the plate, a conductive layer on the first diaphragm, and a second conductive layer on the plate, the first and second conductive layers being the electrodes of a capacitor whose capacitance varies with the position of the diaphragm relative to the plate.

Capacitive sensor

A digital frequency measurement system including first and second digital differentiators responsive to first and second digital quadrature signals representative of first and second quadrature modulated input signals that represent binary data having a center frequency equal to a predetermined IF frequency for generating first and second differentiated signals, first and second processing circuits responsive to the first and second digital quadrature signals representative of the modulated input signals and the first and second differentiated signals for multiplying the first differentiated signal by the second quadrature digital representation of the input signals and multiplying the second differentiated signal by the first quadrature digital representation of the input signals to provide first and second multiplied signals, a combining circuit responsive to the first and second multiplied signals for generating a density signal having a pulse density proportional to the frequency of the input signals, a digital filter responsive to the density signal for providing an output signal representing the average value of the pulse density, and an envelope detector circuit responsive to the output signal for determining the midpoint of the maximum and minimum signal level representative of the input signals and providing a digital signal that represents the center frequency of the input signals.

Digital frequency measurement system and method with automatic frequency control

A chopped charge pump with matching up and down pulses including a first pair of current sources, a second pair of current sources, and a switching circuit for switching on in a first phase one current source of each pair to provide up current pulses, and the other current source of each pair to provide down current pulses, and switching on in a second phase the other current source of each pair to provide up current pulses, and the one current source of each pair to provide down current pulses to offset error in the current response of the pairs of current sources.

Chopped charge pump

A DAC architecture is provided which is monotonic in operation despite any mismatches in the components. The architecture is a segmented architecture and hence it is area efficient. This is achieved by effecting a generation of analog voltages by driving current sources to resistors in response to digital input. In a preferred embodiment, the invention provides a resistor string coupled between output and vref-, and set of current sources. The current sources are switched to nodes between resistors to generate voltages at the output.

DAC having switchable current sources and resistor string

A phase detection apparatus is described for use in a phase lock loop (PLL). The apparatus has a first input for a reference signal, a second input for a loop feedback signal and an output for the phase difference signal. Two D-type flips flops are provided, the first being clocked with the reference signal and the second with the loop feedback signal. The output of the second flip-flop is delayed relative to the first flip-flop, thereby effecting minimal overlap, when using the phase detection apparatus in a fractional- N phase lock loop, of the interpolator activity with that of the charge pump.

Phase frequency detector with adjustable offset

An indirect variable frequency synthesiser for synthesising selectable frequencies from a reference frequency including a multi-divisor programmable frequency divider located in a feedback loop of the frequency synthesiser for dividing the feedback frequency in the feedback loop, the divider being responsive to a varying control signal applied thereto representative of a rational number of selectable value for selecting the divisor thereof for fractional division of the feedback frequency. A variable modulus interpolator converts a fractional part of the rational number of selectable value to a varying digital code representative of the fractional part of the rational number. The variable modulus interpolator includes an Nth order sigma-delta modulator having N sigma-delta stages cascaded in MASH configuration, where N is an integer greater than one, and is responsive to a selectable value of a numerator and a selectable value of a denominator of the fractional part of the rational number for outputting the varying digital code. A primary summer sums a digital code representative of a selectable value of the integer of the rational number with the varying digital code from the variable modulus interpolator to produce the varying control signal for applying to the programmable frequency divider.

Variable modulus interpolator, and a variable frequency synthesiser incorporating the variable modulus interpolator

A variable modulus interpolator () for interpolating a fractional partof a rational number by which a reference frequency is to be divided in a multi-divisor divider in a variable frequency synthesizer comprises a third order sigma-delta modulator () of MASH cascade configuration having first, second and third sigma-delta stages (). The numerator F of the fraction is selectable and is inputted to a first register () for inputting to the input of the first sigma-delta stage () of the sigma-delta modulator (). The denominator M of the fraction is selectable and is inputted to a second register. A single bit output quantiser () in each sigma-delta stage () outputs a sign bit indicative of the sign of the output from an integrator () in the corresponding sigma-delta stage (). A multiplier () is located in the negative feedback loop of each sigma-delta modulator for multiplying the output of the quantiser () being fed back by the denominator M stored in the second register (). The negative of the fed back product of the multiplier and the quantiser output is summed in a first summer () in the corresponding sigma-delta stage () with the input to that stage, and is applied to the integrator (). Quantiser noise from the first and second stages () form the input to the first summers () of the second and third sigma-delta stages (). The outputs of the respective sigma-delta stages () are summed together in an intermediate summer () and in a main summer () to provide a varying digital code for applying to a control input of a multi-divisor divider for providing varying values of divisors for fractional division. The variable modulus interpolator () is particularly suitable for use in conjunction with an indirect frequency synthesizer, and by varying the value of the denominator M the frequency step size between selectable frequencies can be varied.

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Castletroy, Ireland

William Hunt