Google Inc.

William Hang

Jeffrey Adgate Dean

Chian-Min Richard Ho

Azalia Mirhoseini

Emre Tuncer

Anna Darling Goldie

Mustafa Nazim Yazgan

Ya Wang

Anand Babu

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

Generating integrated circuit floorplans using neural networks

Growing community of inventors

Stanford, CA, United States of America

William Hang