Telefonaktiebolaget Lm Ericsson (publ)

William Hallberg

Christian Fager

Rob Maaskant

Mustafa Özen

Marianna Ivashina

Oleg Iupikov

System including a dual-fed antenna element is designed to present 2×2 port impedances that guarantee high efficiency operation of the main- and auxiliary transistors at peak- and backed off power. The proposed solution eliminates the need for lossy power combining, such as PCB based circuit combining or impedance matching networks between the antenna element and the main- and auxiliary amplifiers. The power from the main- and auxiliary transistors are combined at the circuit level by the antenna element.

Integrated active Doherty antenna transmitter

It is provided an amplifier arrangement for optimizing efficiency at a peak power level and a back-off power level &#x3b3;. The amplifier arrangement comprises an input power splitter dividing an input signal into a first signal having a power Pand a second signal having a power P, a main transistor operating in a class-B like mode receiving the first signal, an auxiliary transistor operating in a class-C mode receiving the second signal. The received first and second signals have a phase offset value &#x3b8;, wherein &#x2212;&#x3c0;&#x3c;&#x3b8;&#x3c;&#x3c0;. The amplifier arrangement further comprises a combining network. Circuit element values of the combining network, the power Pand the power P, the phase offset value &#x3b8;, a bias condition of the auxiliary transistor; and a relative size Sof the auxiliary transistor, are based on a predetermined back-off power level &#x3b3;, a current scaling factor rof the auxiliary transistor, a main transistor oversizing factor r, and an auxiliary transistor oversizing factor r, where r&#x3c;1, r&#x2267;1 and r&#x2267;1. It is also provided a method for determining properties for an amplifier arrangement.

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Mölndal, Sweden

William Hallberg