Alcatel Network Systems, Inc.

William H Stephenson, Jr

William B Weeber

William E Powell

Richard W Peters

Richard Marion Czerwiec

Joseph E Sutherland

Timothy J Williams

Joseph Lee Smith

Michael J Gingell

Claude M Hurlocker

Ertugrul Baydar

Raymond E Tyrrell

Dale L Krisher

William J Fox

Gus C Sanders, Jr

Richard J Sanders, Jr

Stephen C Dunning

Hal A Thorne

Francis G Noser

Jak Yaemsiri

Keith L Bernhardt

Jeffrey P Jones

Camille A Abu-Saba

Michael Sutton

O Lamar Bishop

M Rodney Briscoe

Kenneth J Stoia

V Paul Runyon

Heinrich T Sonnenberg

Patrick M Farrell

Victor W Wilkerson

Mohammad S Arani

Dana Merrill

Wenkwei Rou

An asynchronous parallel data formatter for use in mapping low speed serial asynchronous data signals into a higher speed signal includes a set of latches that receive the data from an elastic store. A time domain multiplexer receives signals from the latches as well as signals from an adder is responsive to one or more signals indicative of a need to recirculate data that provides stuff control signals and a carry signal. A formatter receives signals output from the time domain multiplexer and provides stuff and control bits as needed to complete the payload signal. The present asynchronous parallel data formatter provides sequential data transfer of full data bytes into partial bytes using one clock and a single set of control circuitry.

Asynchronous parallel data formatter

Apparatus for converting a DS3 digital signal in a DS3 frame format to a STS-1 digital signal in an STS-1 frame format as a function of a STS-1 local clock. DS3 AIS/Idle code generation means generates DS3 AIS/Idle code bytes in response to the local STS-1 clock signal. DS3 byte counter counts the DS3 AIS/Idle code bytes and generating an AIS/Idle bytecount enable control signal if the number of DS3 AIS/Idle code bytes is less than a predetermined number of DS3 bytes to be mapped in a given row of the STS-1 frame. STS-1 row counter counts pulses of the STS-1 local clock signal and generates a gapped STS-1 enable control signal, which is combined with the AIS/Idle bytecount enable control signal fed back to enable and disable the DS3 AIS/Idle code generation means for mapping DS3 AIS/Idle code bytes in the given row of the STS-1 frame. In a preferred embodiment the DS3 byte counter comprises a plurality of flip-flops and associated combinatorial logic for counting the DS3 AIS/Idle code bytes, and has combinatorial logic for receiving inputs from the plurality of flip-flops for generating an AIS/Idle bytecount enable control signal. The STS-1 row counter has a plurality of flip-flops and associated combinatorial logic for counting pulses of the STS-1 local clock signal, and has combinatorial logic which receives inputs from the plurality of flip-flops for generating a gapped STS-1 enable control signal. The apparatus also has a short row control signal generator for generating a short row control signal to the DS3 byte counter.

Parallel DS3 AID/Idle code generator

A partial word to full word parallel data shifter comprises 2N-1 multiplexer for selectively receiving data from the incoming current data word of width up to N, or from remainder bits of previously received data. The multiplexers output their data to 2N-1 latches, N of which output a full parallel data word and N-1 of which can recirculate up to N-1 remainder bits back to the multiplexers. If the number of remainder bits plus the number of data bits for the currently received word is less than N, the bits in the first N latches are not output but rather recirculate to the multiplexers where they are aligned for generating a full N bit output word with the most significant bit(s) of the next incoming parallel data.

Partial word to full word parallel data shifter

A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

Synchronous optical transmission system

A parallel frame synchronization circuit converts an incoming serial bit stream containing frame synchronization information into parallel data words on arbitrary boundaries of fixed bit length. Detectors forming part of the present invention determine from the parallel converted data the presence of synchronization information so as to align the incoming serial data into parallel data aligned on frame boundaries by manipulating parallel words. The present invention is particularly suited for fabrication in complimentary metal oxide silicon (CMOS) technology and in a preferred embodiment is used to synchronize incoming data comporting to the synchronous optical network (SONET) telecommunication standard.

Parallel bit detection circuit for detecting frame synchronization

Growing community of inventors

Raleigh, NC, United States of America

William H Stephenson, Jr