Xicor Corporation

Intel Corporation

William H Owen, Iii

Richard T Simko

Richard D Pashley

Wallace E Tchon

Joseph Drori

Kim R Kokkonen

Sheau-Ming S Liu

Charles H Steele

A current metering circuit is configured as a single stage charge pump for limiting the current level applied to the tunneling regions of an integrated circuit, nonvolatile, floating gate memory cell. The current metering circuit includes a storage capacitor which has one plate pumped by a periodic signal. The other plate of the capacitor is charged from a voltage that is boot-strapped from the voltage that presently exists across the active tunneling region. More particularly, a high voltage is applied to the drain of a transistor whose gate is connected to the tunneling region. The source of this transistor is coupled to a plate of the storage capacitor. This source develops a voltage equal to the present voltage across the load less the turnon threshold of the transistor. When the periodic signal goes low, the storage capacitor is charged from the voltage appearing at the source of this transistor. When the periodic signal goes high, this transistor is biased to turn off and the capacitor discharges through a diode to develop the metered output current. The current amplitude is equal to the product of the capacitance of the storage capacitor, the change in voltage across the capacitor in each cycle and the frequency of the periodic signal.

Current metering apparatus for optimally inducing field emission of

An integrated testing apparatus provides bidirectional coupling of a high voltage either from an internal source on an integrated circuit to a first external pin on the integrated circuit package, or to the output point of said internal source of high voltage from a voltage source external to the integrated circuit package that is coupled to said first external pin, said coupling occurring in response to an enabling signal externally impressed on a second external pin on said integrated circuit package. The testing apparatus is substantially transparent to normal integrated circuit operation when said enabling signal is removed from said second external pin.

Integrated circuit testing apparatus

An integrated circuit system for generating a regulated high voltage tunneling pulse whose voltage level varies as a function of the voltage level needed to initiate tunneling of electrons across one or more dielectric gaps between respective first and second regions. The voltage level of initial electron tunneling is compared with a predetermined voltage margin so as to cause said generated tunneling voltage pulse to have a voltage level equal to the sum of said detected tunneling voltage and said voltage margin. The tunneling voltage pulse is then maintained substantially at this level for a predetermined duration before the tunneling pulse is discharged.

Integrated circuit high voltage pulse generator system

Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems.

Nonvolatile static random access memory system

Integrated circuit system for generating a rise-time regulated and level controlled high voltage pulse utilizing a plurality of diode-connected stages driven by capacitively coupled low voltage clocks. The maximum output voltage may be controlled by a gated diode reference device, which provides a reference voltage independent of power supply voltage. A feedback circuit may be provided which controls the high voltage rise time by modulating the effective low voltage clock amplitude driving the high voltage generator. A MOS logic level interface circuit may also be provided for sensing achievement of the predetermined high voltage level.

Integrated rise-time regulated voltage generator systems

A process for forming an electrical contact region between layers of polysilicon with an integral polysilicon resistor during the fabrication of MOS integrated circuits is disclosed. The contact region which does not require critical alignments, may be formed directly over an active channel or buried (substrate) contact. A silicon nitride mask is formed at the location of the contact region on the first polysilicon layer thereby allowing a thick oxide to be grown on the remainder of the substrate. After removal of the silicon nitride mask, a second polysilicon layer is formed which contacts the first layer at the contact region and defines the resistor. A doping step is used to establish the resistance of the resistor. The process permits the fabrication, by way of example, of a static (bistable) MOS memory cell employing polysilicon loads with an area of approximately 1.5 mils.sup.2.

Process for forming a contact region between layers of polysilicon with

An integrated circuit, metal-oxide-semiconductor (MOS) static random-access memory (RAM) with a power-down mode is described. The bistable memory cells employed in the memory include low conductivity, depletion mode transistors used as loads. 'Zero' threshold voltage devices are employed on a low body-effect substrate to permit the powering-down of many circuits in the memory without affecting circuit performance. Several circuits employing these zero threshold devices are described.

Low power/high speed static ram

A process and method for accurately defining polycrystalline silicon patterns from a masking member. The critical dimensions of the silicon patterns are controlled by a diffusion step. Self-limiting etching is achieved through use of an etchant which discriminates between doped and undoped polycrystalline silicon. The process which provides significant advantages in production processing, permits fabrication of narrower gates and smoother edges on elongated silicon strips.

Process for defining polycrystalline silicon patterns

A process for fabricating narrow silicon members from a polycrystalline silicon layer, such as gates for MOS field-effect transistors. The edge of a mask is used to define a gap which exposes a narrow line on the underlying silicon layer. A doped region is formed in the silicon layer through the gap and then the layer is selectively etched. The critical dimensions of the fabricated silicon members are determined by the extent of diffusion of the dopant and are substantially independent of masking tolerances.

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Mountain View, CA, United States of America

William H Owen, Iii