E-systems, Inc.

United States of America As Represented by the Secretary of the Air Force

Ncr Corporation

B-systems, Inc.

William H Mosley, Jr

Carl F Andren

David E Sanders

Lex A Scott

Robert S Gordy

Ramon P Chambers

George P Bortnyk

Richard E Roberson

Eugene R Wade

Eric C Heinrich

A detector (20) is provided for use in a communication receiver where a received spread spectrum data signal is detected using a locally generated reference signal to decode the data signal. The detector (20) includes first (22) and second channels (24) and circuitry (90) for applying the received encoded data signal to the first (22) and second channels (24). A local generator (50) is provided for generating the reference signal wherein the reference signal has polarity transitions. A demodulator (40) is included in the first channel (22) for generating a detected recovered data signal from the received data signal in response to the reference signal. Circuitry (52) is provided for detecting the polarity transitions in the reference signal and for generating a differential PN signal. Circuitry (42) is further provided in the second channel (24) for correlating the received data signal and the differential PN signal to thereby generate a recovered error signal. The recovered data signal and the recovered error signal are correlated by circuitry (58) to generate a control signal for application to the local generator (50) for locking the reference signal to a component of the received data signal.

Coherent spread spectrum pseudonoise tracking loop

A method and apparatus for baseband synchronizing of a local PN code sequence with a received PN code sequence incorporated in a received spread spectrum signal is provided. The received spread spectrum signal is translated to baseband to produce an I (in-phase) channel baseband signal and a Q (quadrature-phase) channel baseband signal. Data and error baseband correlators correlate the I channel and Q channel baseband signals with in-phase and quadrature-phase PN signals incorporating the local PN code sequence to produce despread on-time, advanced and delayed I channel and Q channel baseband signals. These despread baseband signals are processed and combined to produce an error signal proportional to a difference between the local PN code sequence and the received PN code sequence. A numerically-controlled oscillator circuit is responsive to the error signal to advance or delay the phase of a reference PN clock signal used to form a local PN clock signal. In operation, the rate of reading the local PN code sequence is accelerated or retarded to synchronize the local and the received PN code sequences.

Method and apparatus for baseband tracking of a PN code sequence in a

A method and apparatus for phase modulating a carrier signal to convey an information signal (12) such that the carrier signal has a constant amplitude envelope. A Hilbert transform signal (14) of the information signal (12) is produced. The signals (12, 14) are sampled to produce signals (16, 18), which represent cartesian coordinate values. The cartesian coordinate values are then converted into equivalent polar vectors (20-36) which have both an amplitude (R) and an angle (.theta.). The polar vector quantity (R, .theta.) is converted into two unity amplitude vectors (A, B). The unity amplitude vectors (A, B) are offset from the polar vector quantity by an angle the cosine of which is proportional to the amplitude of the polar vector (R). The carrier signal is sequentially phase modulated phase angles of the unity amplitude vectors (A, B) for each sample period of the information signal. This modulation procedure maintains a constant amplitude envelope for the carrier signal and makes possible simultaneous demodulation of a plurality of carrier signals in a single demodulation channel.

Method and apparatus for pulse angle modulation

A modulating circuit (10) receives a UHF carrier signal together with a digital input signal for data along with a data clock. A channelizer circuit (60) produces I and Q channel digital data signals derived from the digital input signal. The I and Q channel signals are utilized to trigger one shot circuits (70, 72, 74 and 76) to produce positive and negative pulses corresponding to the signal transitions of the input signals thereto. These pulse signals are provided to integrate and hold circuits (80, 82) which serve to have positive and negative integration, thereby producing ramp signal segments in place of the sudden transitions of the rectangular digital input signals. The resulting data signals from the integration process are passed through diode shaper circuits (82, 92) and low pass filters (88, 94) to produce spectrum shaped I and Q channel modulating signals which have a limited bandwidth. The modulating signals are input to mixers (36, 40) together with respective in-phase and quadrature phase carrier signals to provide amplitude and phase modulation of the carrier signals. The resulting amplitude and phase modulated carrier signals are combined in a summation circuit (44) to produce a resulting modulated, band limited carrier signal.

Method and apparatus for producing a shaped spectrum modulating signal

A method and apparatus for phase modulating a carrier signal to convey an information signal (12) such that the carrier signal has a constant amplitude envelope. A Hilbert transform signal (14) of the information signal (12) is produced. The signals (12, 14) are sampled to produce signals (16, 18), which represent cartesian coordinate values. The cartesian coordinate values are then converted into equivalent polar vectors (20-36) which have both an amplitude (R) and an angle (.theta.). The polar vector quantity (R,.theta.) is converted into two unity amplitude vectors (A, B). The unity amplitude vectors (A, B) are offset from the polar vector quantity by an angle the cosine of which is proportional to the amplitude of the polar vector (R). The carrier signal is sequentially phase modulated by each of the angles of the unity amplitude vectors (A, B) for each sample period of the information signal. This modulation procedure maintains a constant amplitude envelope for the carrier signal and makes possible simultaneous demodulation of a plurality of carrier signals in a single demodulation channel.

A baseband correlation circuit (10) receives an IF spread spectrum input signal which is phase compared with a local oscillator signal and a phase shifted local oscillator signal to produce I channel and Q channel spread baseband signals. Each of these signals is input to four sample and hold circuits (34-48). A local PN code signal is converted from two-phase to four-phase to produce I and Q channel local PN signals. These signals together with the logical inverses thereof are provided as the control inputs for the sample and hold circuits (34-48). For each pair of sample and hold circuits there is a respective summer (86-92). The pair of sample and hold circuits together with the corresponding summer comprises a double balanced multiplier. There are four double balanced multipliers for producing four respective product signals. The product signals are input as pairs into summers (106) and (108) to produce despread, narrowband baseband I and Q channel output signals at output lines (110, 112). The baseband correlator circuit (10) of the present invention serves to despread the spread spectrum IF signal at baseband, thereby eliminating the need for costly and bulky components which are required for despreading at RF frequencies.

Method and apparatus for despreading a spread spectrum signal at baseband

A segmented, transversal correlator for use in a spread spectrum communications system accurately synchronizes to an incoming spread signal by passively searching for a particular section of a known reference PN code sequence. To achieve correlator lengths of greater than one data bit long, the correlator may comprise a plurality of correlation subsections, each including a loading register for storing a different section of the overall reference PN code sequence. A section of the PN code sequence is transferred into a circulating register in each subsection through a parallel transfer. The dynamic, circulating PN code sequence is then correlated against statically stored analog samples of the incoming spread signal. When the dynamic PN reference code sequence is aligned with the corresponding PN sequence in the analog samples, a correlation signal is produced and magnitude detected to form a signal which is applied to a summation circuit. The summation circuit receives the outputs of each of the correlator subsections and produces a correlation output signal for the entire correlator.

Transversal correlator

A transversal correlator is disclosed for demodulating a phase shift keyed (PSK) signal. The PSK signal is mixed with a local oscillator signal to produce quadrature I-channel and Q-channel signals. The I-channel and Q-channel signals are sampled at a periodic rate and the samples are propagated through a shift register for each channel. A preselected pseudo noise signal is stored in a local register which has an output tap for each stage. Each of the analog shift registers has a stage corresponding to one of the stages of the local register. Each of the I-channel and Q-channel samples is multiplied by the binary state in the corresponding stage of the local register. This multiplying operation produces a plurality of product signals. Product signals for alternate samples of the I-channel signal are summed with alternate but offset samples of the Q-channel signal to produce a first summation signal. The remaining alternate samples of the I-channel and Q-channel signals are also summed to produce a second summation signal. The first and second summation signals are full wave rectified then summed to produce a correlation output signal.

Simplified transversal correlator for MSK and MSK related waveforms

A recovery loop includes an analog circuit that mixes a fixed frequency signal from a temperature controlled oscillator (20) with an IF input to produce product signals corresponding to the quadrature components of data signals with frequency offset. A digital complex multiplier (32) is responsive to the product signals and to the output of a number controlled oscillator (34) to produce a digital output corresponding to the data signals. The output of the number controlled oscillator (34) is controlled by a digital phase lock loop.

Digital baseband carrier recovery circuit

Three sample and hold circuits (26, 30 and 34) sample a received pulse amplitude modulated signal at twice the data bit frequency or timing of the received signal. The clock to the sample and hold circuits is timed so that three consecutive samples, two mid-bit samples and a transition sample are held in the circuits (26, 30 and 34) once every two sample periods. The mid-bit samples are added together by an adder (32) and divided by two in a divider (38) to provide an average. The transition sample is subtracted from this average in a subtractor (36) to produce an error signal. The error signal is normalized in a multiplier (44) using the reciprocal of the difference in magnitude between the two mid-bit samples to produce a normalized signal. A clock signal is generated by a voltage controlled oscillator (52) in response to the normalized signal at twice the bit frequency or bit timing and in synchronism therewith.

Phase locked loop for recovering data bit timing

A phase lock loop (10) includes a frequency and phase preset network for presetting a local oscillator (20) in substantial synchronism with a carrier signal. The preset network utilizes time delayed output signals from split or double correlators (32, 34, 36, 38) to determine a change in the phase angle between the local oscillator signal and the carrier signal for a known time period to determine the frequency of the local oscillator signal relative to the carrier signal frequency. The preset network determines the phase of the local oscillator signal relative to the carrier signal phase utilizing the summed output of one split correlator (32 and 34) and of another split correlator (36 and 38).

Preset network for a phase lock loop

A direct current responsive mixing circuit (10) includes three mixers (14, 16 & 18), each having one D.C. port and two A.C. ports. The D.C. ports are responsive to D.C. and A.C. signals, while the A.C. ports are responsive only to A.C. signals. One mixer (14) has an A.C. port (24) receiving a pump signal and a D.C. port (28) receiving an I input signal. A second mixer (16) has an A.C. port (26) receiving the pump signal and a D.C. port (32) receiving a Q input signal. The remaining A.C. ports of the first two mixers (14 and 16) are connected to the two A.C. ports (36 and 38) of the third mixer (18). An output signal having a component corresponding to the product of the I and Q input signals is produced at the D.C. port (40) of the third mixer (18). In this construction, the mixing circuit 10 is responsive to A.C. and D.C. input signals and may produce a D.C. output signal component.

Double balanced diode mixer with d.c. response

A biphase shift keyed modulated carrier is input to an analog delay line having a plurality of sampling taps time spaced along the line. The modulated input carrier is sampled at a rate four times the carrier frequency to produce amplitude samples of the input. The taps of the delay line are divided into two groups comprising alternate tap sets and the amplitude samples of each group are summed for decoding the I and Q channels of a modulated carrier. The summed signal of each of the channels is input to an individual sample and hold circuit which aliases the carrier frequency to baseband. The output of the first sample and hold circuit of each channel is provided to a second sample and hold circuit for the respective channels. The second sample and hold circuit of each channel is clocked at a data rate derived from a bit timing loop. An estimation of the data is produced by each of the second sample and hold circuits with the data produced by the second sample and hold circuit of one channel providing a recovered carrier signal output. Further, the data produced by each of the second sample and hold circuits, after inversion in one line by means of an inverting amplifier, is input to a phase comparator. The output of the phase comparator is filtered and used to drive a voltage controlled oscillator that generates the clock pulses to operate the first sample and hold circuits and also to clock the delay line.

Phase/frequency controlled phase shift keyed signal carrier

A variable frequency oscillator is disclosed wherein the magnitude of a signed digital input determines the output frequency. The variable oscillator includes a digital integrator circuit for performing a modulo 2.pi. digital integration of the input signal. The integrator circuit is connected to a digital quadrature circuit which converts the integrated input signal from its polar form into two digital control signals in the rectangular domain having a quadrature phase relationship. The control signals are utilized in analog form by their combination with a high frequency carrier and its quadrature phase to synthesize the desired output frequency in an analog embodiment. According to another embodiment the quadrature synthesis is provided by the digital combination of the control signals and the phased carrier components.

Digitally controlled variable frequency oscillator

A nonlinearly variable gain circuit is utilized to produce an inverted logarithmic S curve of gain versus potentiometer rotation while using a linear resistance taper potentiometer. An operational amplifier feedback circuit uses the linear potentiometer and a resistance network in combination.

Growing community of inventors

St. Petersburg, FL, United States of America

William H Mosley, Jr