Applied Materials, Inc.

William H McClintock

Wen-Chiang Tu

Boguslaw A Swedek

Fred Conrad Redeker

Hassan G Iravani

Zhihong Wang

Zhefu Wang

Mei Yin Chang

Nitin K Ingle

Rajeev Bajaj

Feng Quan Liu

Robert B Lowrance

Deenesh Padhi

Bok Hoen Kim

Barry Lee Chin

Zheng Yuan

Xinliang Lu

Chien-Teh Kao

Daniel Redfield

Yi Zheng

Lakshmanan Karuppiah

Jason Garcheung Fung

Yuchun Wang

Howard E Grunes

Wei Guang Lu

Zhenbin Ge

You Wang

Vikash Banthia

Jing Tang

Josephine Juhwei Liu

Anthony Konecni

Wei Lu

Embodiments disclosed herein provide methods of forming bond pad redistribution layers (RDLs) in a fan-out wafer level packaging (FOWLP) scheme using an additive manufacturing process. In one embodiment, a method of forming a redistribution layer includes positioning a carrier substrate on a manufacturing support of an additive manufacturing system, the carrier substrate including a plurality of singulated devices, detecting one or more fiducial features corresponding to each of the plurality of singulated devices, determining actual positions of each of the plurality of singulated devices relative to one or more components of the additive manufacturing system, generating printing instructions for forming a patterned dielectric layer based on the actual positions of each of the plurality of singulated devices, and forming the patterned dielectric layer using the printing instructions.

Integrating 3D printing into multi-process fabrication schemes

A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.

Substrate features for inductive monitoring of conductive trench depth

Embodiments described herein relate to removing material from a substrate. More particularly, the embodiments described herein relate to polishing or planarizing a substrate by a chemical mechanical polishing process. In one embodiment, a method of chemical mechanical polishing (CMP) of a substrate is provided. The method comprises exposing a substrate having a conductive material layer formed thereon to a polishing solution comprising phosphoric acid, one or more chelating agents, one or more corrosion inhibitors, and one or more oxidizers, forming a passivation layer on the conductive material layer, providing relative motion between the substrate and a polishing pad and removing at least a portion of the passivation layer to expose a portion of the underlying conductive material layer, and removing a portion of the exposed conductive material layer.

Chemical planarization of copper wafer polishing

A method and apparatus for forming an amorphous carbon layer on a substrate is provided. A first portion of the amorphous carbon layer having a high stress level is formed from a hydrocarbon precursor having high dilution ratio, with optional amine precursor included to add stress-elevating nitrogen. A second portion of the amorphous carbon layer having a low stress level is formed on the first portion by reducing the dilution ratio of the hydrocarbon precursor and lowering or eliminating the amine gas. Pressure, temperature, and RF power input may be adjusted instead of, or in addition to, precursor flow rates, and different precursors may be used for different stress levels.

Composite removable hardmask

A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space.

Methods of thin film process

A robot assembly including multiple independently operable robot assemblies are provided for use in semiconductor wafer processing. The robot assembly includes independent co-axial upper and lower robot assemblies adapted to handle multiple objects. The upper robot is stacked above the lower robot and the two robots are mounted concentrically to allow fast wafer transfer. Concentric drive mechanisms may also be provided for imparting rotary motion to either rotate the robot assembly or extend an extendable arm assembly into an adjacent chamber. Each robot can be either a single blade robot or a dual blade robot. Also provided is an apparatus for processing semiconductor wafers comprising a pre/post process transfer chamber housing multiple independent robot assemblies and surrounded by a plurality of pre-process chambers and post process chambers. Within each process, pre-process and post-process chamber is an apparatus for holding a plurality of stacked wafers. The apparatus includes a wafer lifting and storing apparatus exhibiting a plurality of vertically movable lift pins surrounding the chamber pedestal. The lift pins are configured to receive and hold a plurality of stacked wafers, preferably two, therein.

Multiple independent robot assembly and apparatus for processing and

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Los Altos, CA, United States of America

William H McClintock