International Business Machines Corporation

William H Guthrie

William R Tonti

John Atkinson Fifield

Richard Steven Kontra

Wayne S Berry

Jack Allan Mandelman

John Edward Cronin

James Gardner Ryan

Robert Michael Geffken

Oliver Kiehl

Rosemary A Previti-Kelly

Josef S Watts

Carter W Kaanta

Ronald R Uttecht

Duane E Galbi

Andrew J Watts

Edward John Dombroski

Richard W Noth

Michael Ruprecht

Andreas Kluwe

Paul A Farrar, Sr

James A Bilowith

A programmable device includes a substrate (); an insulator () on the substrate; an elongated semiconductor material () on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end () is substantially wider than the second end (), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

Programmable semiconductor device

A method for manufacturing integrated circuits (&ldquo;IC&rdquo;) on wafers to manage crack damage in the ICs such that crack propagation into the IC active array is reduced or eliminated. The method provides for a defined separation or divide of the IC gate conductor from the IC crack stop or IC edge. The method is especially useful in managing crack damage induced through the delamination of one or more of the gate conductor surface interfaces as a result of the IC wafer dicing process. Circuits or chips manufactured according to the methods disclosed are also taught.

Method for eliminating crack damage induced by delaminating gate conductor interfaces in integrated circuits

A fuse, having reduced blow-current requirements thereby minimizing the power supply voltage and chip area required for the driver transistors, has a geometry which is characterized by an essentially uniform width dimension throughout the primary axis of the fuse link but having at least one approximately right angle bend in the fuse link. The fuse can be blown open with approximately 10% of the input current density required for a straight fuse of equal cross-sectional area. The reason for this is that, due to current crowding, the current density is accentuated at the inside corner of the bend. As the input current to the fuse is increased, a current density is reached at the inside corner which causes the fuse material to melt. A notch forms at the inside corner. The fuse geometry altered by the notching causes even more severe current crowding at the notches, and this in turn makes the melting propagate across the width of the fuse. The predictability of the point of fuse blow out allows even greater circuit densities while minimizing the possibility of accidental damage to adjacent devices.

ZAG fuse for reduced blow-current application

A sequence of masking steps reduces the amount of transference of a workpiece among work stations and reduces certain tolerances required for mask alignment in the construction of integrated circuits, and a gray level mask suitable for photolithography. In the integrated circuit, masking layers are developed directly in a wafer for delineating vertical and horizontal portions of an electrically conductive path. The mask is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. Both the wafer and the mask are fabricated by a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist and other ones of the layers. The etches include plasma etch with chloride ions to attack the chromium of the opaque layer, compounds of fluorine to attack the glass layer, and reactive ion etching with oxygen to attack the photoresist structure.

Plural level chip masking

Multiple, single conductor, tape automated bonding (TAB) tapes are sequentially applied to a semiconductor device by the bonding of a first, etched, single layer TAB tape to an outer row of bonding pads on a semiconductor chip and to selected contacts on a lead frame followed by the laying down of at least one additional etched, single layer TAB tape which is then bonded to an inner row of bonding pads on the semiconductor chip and to different selected lead frame contacts. If desired the subsequent TAB tape may be adhered to the preceding TAB tape to increase the mechanical strength of all the tapes and improve the electrical characteristics of the tapes. The application of one or more ground planes to the assembly is also shown.

Tape bonded semiconductor device

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Essex Junction, VT, United States of America

William H Guthrie