W. L. Gore & Associates, Inc.

Other

Supercomputer Systems Limited Partnership

William George Petefish

Paul J Fischer

Mark F Sylvester

David B Noddin

John J Budnaitis

David A Hanson

Boydd Piper

Robin E Gorrell

Michael R Leaf

Jimmy Leong

Deepak N Swamy

Kevin L Stumpe

Thomas E Walker

A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.

Constraining ring for use in electronic packaging

A method of minimizing warp and die stress in the production of an electronic assembly includes connecting one surface of a die to a package, and connecting an opposite surface of the die to a lid disposed over a constraining ring that is mounted to the package. The lid has a size, shape and coefficient of thermal expansion (CTE) selected to generate a bending moment that opposes bending moments resulting from connecting the die to the package.

Method for minimizing warp and die stress in the production of an

A method and apparatus are provided for aligning and laminating stiffeners to substrates in electrical circuits. Generally, this method includes placing a substrate within an alignment frame or tool; applying an adhesive on the substrate; placing a stiffener on the adhesive to form a chip package; applying sufficient pressure and heat to the package for a sufficient time to cure the adhesive. Another method of the present invention includes placing a substrate within an alignment tool or frame; applying an adhesive on the substrate within the alignment tool; placing a stiffener on the adhesive to form a package; applying sufficient heat and pressure to the package for a sufficient time to tack the stiffener to the substrate; removing the package from the alignment tool or frame; and heating the package for a sufficient time and temperature to cure the adhesive wherein the stiffener enhances rigidity of the package.

Method for aligning and laminating substrates to stiffeners in

A method of making a laminated structure includes forming a first lamination having first and second conductive layers having inner and outer surfaces and being spaced apart by a dielectric layer, drilling through the first conductive layer and dielectric layer to form a blind via having a bottom coexistent with the inner surface of the second conductive layer, plating the blind via with a conductive material, and patterning the second conductive layer to form at least one contact pad over the blind via.

Method and apparatus for improving wireability in chip modules

A method and apparatus are provided for coining solder balls on an organic electrical circuit package. Generally, this method includes placing a slug on one or more of the solder balls; and applying sufficient pressure for a sufficient period of time on the slug to flatten the surface of the solder balls so as to form planar solder coins. The apparatus includes a press; a ram attached to the press; a platform for receiving the package and a slug placed upon the solder balls.

Method for coining solder balls on an electrical circuit package

An integrated circuit package for housing an integrated circuit (IC) chip and providing electrical connectivity of data signals and voltage signals between the IC chip and an electronic component includes a substrate, an IC chip affixed to the substrate and at least three conductive layers on the substrate. The three conductive layers include at least a first voltage layer adjacent to the substrate for providing a first reference voltage signal (i.e., ground) to the IC chip, a second voltage layer for providing a second reference voltage signal (i.e., power) to the IC chip, and a signal layer. To maximize speed and minimize complexing all of the data signals to the IC chip are routed on the signal layer. The power and ground layers are closely coupled and separated by a dielectric layer having a relatively high dielectric constant for providing significant decoupling capacitance. A low dielectric layer is provided for separating the power layer from the signal layer. A plurality of electrical connections interconnect bonding pads on the IC chip with the electronic component (e.g., a PCB) by way of at least one of the conductive layers.

Integrated circuit package

An integrated circuit package for housing an integrated circuit (IC) chip and providing electrical connectivity of data signals and voltage signals between the IC chip and an electronic component includes a substrate, an IC chip affixed to the substrate and at least three conductive layers on the substrate. The three conductive layers include at least a first voltage layer adjacent to the substrate for providing a first reference voltage signal (i.e., ground) to the IC chip, a second voltage layer for providing a second reference voltage signal (i.e., power) to the IC chip, and a signal layer. To maximize speed and minimize complexing, all of the data signals to the IC chip are routed on the signal layer. The power and ground layers are closely coupled and separated by a dielectric layer having a relatively high dielectric constant for providing significant decoupling capacitance. A low dielectric layer is provided for separating the power layer from the signal layer. A plurality of electrical connections interconnect bonding pads on the IC chip with the electronic component (e.g., a PCB) by way of at least one of the conductive layers.

A method and apparatus for manufacturing large area multilayer interconnects for electronic substrates and circuit boards uses high density area array interconnections that are created by solid state diffusion. Two or more pretested subsections are electrically and mechanically joined together to simultaneously form a multilayer substrate without employing a flow-type connection where the conductive interconnect material is entirely in a liquid phase at some point during the joining process. Each substrate is comprised of a planar dielectric substrate having a plurality of conductive layers. On at least one surface of the substrate a conductive pad lay is formed having a plurality of interconnect pads. The interconnect pads are positioned at a uniform height above the surface of the dielectric substrate and include a base metal layer, a top metal layer with at least one of the conductive pad layers have a donor metal disposed on top of the top metal layer. When the conductive pad layers of two or more subsections are aligned and stacked together, the interconnect pads can be mechanically and electrically joined together using solid state diffusion to join the donor metal layer and the top metal layer to form an area array interconnection without bonding the surrounding dielectric substrate.

Growing community of inventors

Eau Claire, WI, United States of America

William George Petefish