Cirrus Logic Inc.

Edgewater Computer Systems, Inc.

William Gardei

Douglas F Pastorello

Frank Den Breejen

Bruce Philip Del Signore

Eric T King

Amit Sinha

William James Torke

David Michael Biven

Victor Aguilar

An apparatus and method for performing digital timing recovery includes a rotating demultiplexor receiving a four times oversampled baseband signal and providing four downsampled phases at respective outputs. Each output is processed by a correlation detector which computes a peak sum signal for each downsampled phase. The peak sum signals are processed to produce a best phase select output signal. The best phase select output signal is used to select the optimum sampling phase. Symbol timing is then determined based on the relative peak offset in the best downsampled phase.

Method and apparatus for performing digital timing recovery on oversampled 802.11b baseband signals

An integrated circuit, in which one or more internal parameters may be automatically configured for a particular application, includes a plurality of program select pins, each being in a predetermined fixed state, and at least one configuration pin associated with a parameter to be adjusted. Jumpers on the system board to which the integrated circuit is mounted connect the mounting pad of each configuration pin with the mounting pad of a selected program select pin. Consequently, when the integrated circuit is mounted on the system board, each configuration pin receives a selected value which internal configuration circuitry detects and causes the corresponding parameter to be adjusted accordingly. Any of the program select pins may have functions in addition to the configuration function. When the system board is powered on or undergoes a reset, a processor internal to the chip scans each the configuration pin to determine its value. The processor then sets internal registers accordingly, completing the configuration process, and the chip may begin normal operation.

Integrated circuit with authomatic pin-strapping configuration

A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system further includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value. The method further includes further delaying production of the selected signal with a second comparison utilizing a second predetermined value of a further reduced frequency clock.

Delay systems and methods using a variable delay SINC filter

An analog to digital converter system includes first and second delta sigma converters, a calculation engine, and a serial interface on a single chip. The calculation engine is configured to calculate energy, power, rms current and voltage for single phase or wire power meters. Voltage and current are measured with a shunt or transformer, and a divider or transformer, respectively. The serial interface is bidirectional for communication with a microprocessor or controller, and provides a fixed width programmable frequency output proportional to energy. The digital converter system is user system calibratible.

Single phase bi-directional electrical measurement systems and methods using ADCs

A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system filter includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value. The method filter includes further delaying production of the selected signal with a second comparison utilizing a second predetermined value of a further reduced frequency clock.

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Derry, NH, United States of America

William Gardei