International Business Machines Corporation

William G Tuel, Jr

Rama Krishna Govindaraju

Su-Hsuan Huang

Robert Michael Straub

Elizabeth Anne Kon

Chulho Kim

Richard R Treumann

Christophe Fagiano

Christophe Lombard

Richard J Coppinger

Gary J Mincher

Patricia E Heywood

Janet Morgan

Christophe Pierre Francois Quintard

A hierarchical fanout connectivity infrastructure is built and used to start a parallel application within a parallel computing environment. The connectivity infrastructure is passed to a checkpoint library, which employs the infrastructure and a defined sequence of events, to perform checkpoint, restart and/or migration operations on the parallel application.

Fanout connectivity structure for use in facilitating processing within a parallel computing environment

A method for implementing Message Passing Interface (MPI-2) one-sided communication by using Low-level Applications Programming Interface (LAPI) active messaging capabilities, including providing at least three data transfer types, one of which is used to send a message with a message header greater than one packet where Data Gather and Scatter Programs (DGSP) are placed as part of the message header; allowing a multi-packet header by using a LAPI data transfer type; sending the DGSP and data as one message; reading the DSGP with a header handler; registering the DSGP with the LAPI to allow the LAPI to scatter the data to one or more memory locations; defining two sets of counters, one counter set for keeping track of a state of a prospective communication partner, and another counter set for recording activities of local and Remote Memory Access (RMA) operations; comparing local and remote counts of completed RMA operations to complete synchronization mechanisms; and creating a mpci_wait_loop function.

Method for implementing MPI-2 one sided communication

Messages arriving at a receiver are managed to ensure proper ordering of the messages. To facilitate proper ordering, a message sequence number is used, as well as matching criteria to match a correctly sequenced message with a posted receive. In response to processing a message, a check is made as to whether previously out of order messages can now be processed.

Managing message arrival to ensure proper matching of unordered messages

Method, computer program product, and apparatus for efficiently dispatching threads in a multi-threaded communication library which become runnable by completion of an event. Each thread has a thread-specific structure containing a 'ready flag' and a POSIX thread condition variable unique to that thread. Each message is assigned a 'handle'. When a thread waits for a message, thread-specific structure is attached to the message handle being waited on, and the thread is enqueued, waiting for its condition variable to be signaled. When a message completes, the message matching logic sets the ready flag to READY, and causes the queue to be examined. The queue manager scans the queue of waiting threads, and sends a thread awakening condition signal to one of the threads with its ready flag set to READY. The queue manager can implement any desired policy, including First-In-First-Out (FIFO), Last-In-First-Out (LIFO), or some other thread priority scheduling policy. This ensures that the thread which is awakened has the highest priority message to be processed, and enhances the efficiency of message delivery. The priority of the message to be processed is computed based on the overall state of the communication subsystem.

Thread dispatcher for multi-threaded communication library

A method for transparently handling messages originating from local shared memory and from an external source. A device driver allows the local sender to identify and wake up a waiting receiver task thread, simulating a packet arrival hardware interrupt. Upon awakening, the receiver task thread examines both shared memory and hardware message queues. The method can use a software routine that simulates handling of an occurrence of a hardware interrupt. The method invokes a local notify system service module that passes a window number identifying a receiving task. The method invokes a wake thread module that passes awakens a thread associated with the window number, and examines the shared memory buffer for receipt of the local source message. The method then copies the local source message from the shared memory buffer to the receiving task.

Interrupt mechanism for shared memory message passing

Message-passing capability is provided in a computer system with a plurality of asynchronous computing nodes interconnected for transmission of messages between threaded user tasks executing in ones of the computing nodes. A message is received at a receiver computing node employing a threaded message passing interface (MPI), which includes a means by which a user-defined program can be called by an interrupt service thread at the MPI. The user-defined program takes a predefined action in response to the asynchronous arrival of the at least one message packet. For example, the user-defined program might comprise a program to initiate a function to receive the at least one message packet at the receiver's threaded MPI, which may include awaking a waiting thread.

Method for handling of asynchronous message packet in a multi-node threaded computing environment

System for handling asynchronous message packet in a multi-node threaded computing environment

Handling of asynchronous message packet in a multi-node threaded computing environment

Hybrid lock and unlock capabilities are provided for a threaded computing environment. For example, kernel locking services are selectively employed in conjunction with functions in the POSIX threads standard to provide a lock capability and an unlock capability. The hybrid approach determines which lock scheme to employ by evaluating whether one thread or multiple threads concurrently desire a resource lock. When only one thread desires the lock, the thread is directly assigned resource ownership employing one of an operating system primitive lock process or a hardware lock process. An alternate lock process is used to obtain resource ownership when multiple threads concurrently desire the lock. This alternate process employs at least one function in the POSIX threads standard to implement a queue of waiting threads. A similar hybrid approach to the unlock capability is also provided.

Method for resource lock/unlock capability in multithreaded computer

Resource lock/unlock capability in multithreaded computer environment

System for resource lock/unlock capability in multithreaded computer

A system and method for translating vector description displays into raster images writes the vector description image, having some number of displayable colors, into more than one intermediate image file. Each intermediate image file can define only a number of colors which is smaller than the number of colors in the original display. Separate color translation tables are used to generate each intermediate file. Proper selection of the color translation tables causes each intermediate file to contain a portion of the full color information. The intermediate files are translated to intermediate raster files which are then combined into a single raster image which retains all of the colors of the original vector description image.

Growing community of inventors

Kingston, NY, United States of America

William G Tuel, Jr