International Business Machines Corporation

William G Kempke

Roy L Hoffman

Frank G Soltis

Neil Clair Berglund

John W McCullough

Richard T Turner

William C Richardson

Glen R Mitchell

Merle E Houdek

James Gregory Ranweiler

Eugene R Jones

Richard D Crowley

A method and apparatus are provided to enable interruption of list processing operations in a computer system and to enable restart from the point of interruption. A mechanism, at a predetermined point of the list processing operation, operates to recognize occurrences of interrupting events. If any such events are present, a mechanism saves the status of the list processing operation, saves the identification of the task associated with instruction executing the list processing operation and locks the list or queue. After the interrupt is handled, a mechanism restores status, and unlocks the list or queue only when the identified task is active again and the instruction which had been executing the list processing operation is again executing.

Process and apparatus for interrupting and restarting sequential

A digital computer system including a computation unit (14), a main store (12), a virtual address translator (10), a microinstruction control unit (170) and an instruction code prefetch circuit (212). User instruction codes are stored sequentially in the main store (12) which is accessed for read and write operations by the virtual address translator (10). The instruction code prefetch circuit (212) retrieves the user instruction codes from the main store (12) and holds the instruction codes in a register (16, 18). The instruction codes are transferred from the register (16, 18) to the computation unit (14) in sequential order of use. The microinstruction control unit (170) produces selected microinstructions which are executed by the computation unit (14) to accomplish the operations specified by the user instructions. Designated microinstructions include commands which activate the instruction code prefetch circuit (212) to retrieve the succeeding user instruction codes from the main store (12).

Computer instruction prefetch circuit

Improved task handling apparatus for a computer system where the task dispatcher is selectively operable under instruction control for performing task queue selection and where the intertask communication mechanism can return a task dispatching element (TDE) to a non-prime task dispatching queue (TDQ) as well as to the prime TDQ. Whenever a TDE is returned to the prime TDQ, the task dispatcher makes a pre-emptive task switch. Also, if there are no task dispatching elements on the current non-prime TDQ, the task dispatcher switches to dispatch TDE's from the prime TDQ.

Task handling apparatus

Control circuitry is provided for controlling the generation of a block check word simultaneously with the writing of control words into a transient area of a writeable control storage. The control circuitry in response to a write control storage instruction generates control signals for controlling existing central processing unit (CPU) hardware to effect generation of the block check word while a control word is being written into the transient area of control storage. Microinstructions in the resident area for performing the overlay force selection of a local storage register which has been initialized. The operand from the local storage register is applied to the ALU together with the word which is also being written into control storage. The ALU is forced to perform an exclusive OR operation and the result is returned to the selected LSR. In this manner a block check word is dynamically calculated word by word as each word is written into control storage. When all the control words have been loaded into control storage, a pre-calculated block check word is retrieved from main storage and compared with the calculated block check word. A miscompare indicates that the group of control words written into control storage had been modified when resident in main storage.

Transient microcode block check word generation control circuitry

A control system for a computer includes a control store (30) for storing end op, I-1, I-2 and return words. A microinstruction decode and control unit (170) responds to end op words to initialize and personalize computer components to facilitate subsequent execution of a high level instruction. The control unit (170), in conjunction with a next address logic (162), selects the next microinstruction to be executed in response to a high level instruction. The control unit (170) and logic (162) are responsive to I-1 words to personalize the computer and to select a microinstruction to begin E-phase of a high level instruction. In response to I-2 control words, the control unit (170) and logic (162) select an operand fetch routine in the control store (30), and write a first E-phase address into a local store (138). The return word gates the first E-phase address from the local store (138) to select a microinstruction in the control store (3) to being E-phase.

I-phase controls for a computer

Tagged pointer handling apparatus is provided for implementation in a computer system wherein a tag bit is provided for each word in main storage. This invention provides for the mixing of data and pointers within the same storage space, and provides a capability for checking and verifying the validity of the pointers without affecting the performance or operation of other instructions. Only the tag instructions can set the tag bits ON in main storage; all other instructions store data and set the corresponding tag bits OFF. Thus, if a pointer was modified inadvertently by one of these data handling instructions, the fact that the pointer is untagged is detected and the values in the pointer are treated as invalid when the pointer is used by the Load and Verify Tags instruction. Instructions to load, store, set, move, extract and insert tags are implemented by the tagged pointer handling apparatus. A Load and Verify Tags instruction checks the validity of the pointer and if valid, loads the pointer into a specified general purpose register. A Store and Set Tags instruction stores the value in a specified general purpose register into main storage and sets the associated tag bits ON. A Move and Set Tags instruction moves a word from one location in main storage to another or the same location in main storage and sets the associated tag bits ON. A Move Characters and Tags instruction moves a word and the associated tag bits from one storage location to another storage location. An Extract Tags instruction fetches each word from an operand in main storage, extracts the tag bits, compresses the tag bits to one tag bit per quadword, and stores the tag bits in main storage as data. An Insert Tags instruction fetches the tag bits stored in main storage as data, expands the tag bits to one tag bit per word, and inserts them on each associated word of an operand in main storage.

Tagged pointer handling apparatus

Task handling apparatus in a computer system is structured to be common to system control tasks, user tasks and I/O tasks. Although the task handling apparatus contains a task priority structure, all tasks are handled in the same manner, and there are no fixed interrupt levels for I/O tasks. There are N levels of priority, and N is variable. Each task is a server for a functional request. Task dispatching elements (TDE's) are enqueued in priority sequence on a task dispatching queue (TDQ). A task dispatcher functions to dispatch the highest priority TDE on the TDQ, if any, and to perform task switching. Intertask communication is accomplished by send message, send count, receive message and receive count mechanisms, and is coupled with task synchronization. Task synchronization is achieved by dequeueing and enqueueing TDE's on the TDQ. An active task becomes inactive dispatchable when a higher priority TDE is enqueued on the TDQ by send message or send count mechanisms. The active task becomes inactive waiting when a receive message or receive count is not satisfied. An inactive dispatchable task becomes the active task when it becomes the highest priority enqueued TDE on the TDQ by the receive message or receive count mechanisms. An inactive waiting task becomes either the active task or an inactive dispatchable task after being enqueued on the TDQ by the send message or send count mechanisms, depending upon whether it is the highest or other than the highest priority TDE on the TDQ.

Task handling apparatus for a computer system

A special directly executable instruction, Fetch Instruction Operand Address (FIOA) is accessed in response to encountering a complex non-directly executable instruction. Execution of the FIOA instruction causes generation of control signals for address calculation of the operands in the non-directly executable instruction by the same I phase hardware used by other directly executable instructions.

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Rochester, MN, United States of America

William G Kempke