International Business Machines Corporation

William G Crouse

Malcolm Scott Ware

Donald E Carmon

Albert W Vinal

Earl Albert Cunningham

David R Irvin

Charles R Knox

A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

System for controlling task execution in a host processor based upon the

System for handling requests for DMA data transfers between a host

Multi-media computer system diagnostic system for fault isolation in a multi-tasking hard, real-time task environment is described. Hard, real-time multi-tasking operations, particularly those unique to signal processing tasks may be monitored without creating a task processing overload and without delaying the results beyond hard, real-time task deadlines by insertion of a branch instruction in the task execution instructions being examined which cause execution of the task to branch to a diagnostic program. The diagnostic program executes a diagnostic instruction set and captures one or more digital samples characteristic of the operation of the hard, real-time task at the point in its program execution where the branch instruction was located. The digital data samples so obtained may be queued and graphically plotted on the screen of a display associated with the computer system to generate a graphical representation of the performance of the algorithm or signal processing task under examination in order to quickly isolate task malfunctions without having to review a mass of digital data samples. Alternatively, pre-selected samples may be injected into the task execution by loading task registers with predetermined data by executing a branch to a diagnostic function which inserts the samples.

Multi-media computer diagnostic system

System for constructing a partitioned queue of DMA data transfer

A method and apparatus for controlling the readout rate of information from a sequential storage medium, such as a CD-ROM, to maintain synchronism between the device containing the medium and an independent receiver receiving the information. Information is loaded from the media into a buffer at a rate controlled by pulses from a device clock. Information is unloaded from the buffer for utilization by the receiver independently of the loading of the buffer. The amount of free space available in the buffer is measured as information is loaded into the buffer. The rate of the clock is dynamically adjusted in response to the amount of free buffer space to maintain the full state of the buffer within predetermined limits. In this manner, the buffer never empties or fills in response to the unloading by the independent receiver.

Method and apparatus for synchronizing the readout of a sequential media

A sub-band coder utilizes one or more bit allocation tables to dynamically distribute the channel bit capacity bandwidth among the frequency bands according to the desired output quality of speech rather than by means of complex algorithms or simulation techniques. Multiple bit assignment tables are provided to allow various quality levels to be traded off as increasing bit rate demands are placed upon the transmission system. The technique is used for a single coder to achieve a minimum bit rate for a desired given level of subjective quality in speech output or may be used in a shared bit resource to maintain equal and minimum quality degradation for all users. The quality tables determine the number of bits to be dropped from the encoded representation of each signal sample to minimize the transmission load for a given coder without sacrificing speech quality to an unacceptable degree. Table entries are arranged based on the overall band peak energy level and on the sub-band peak energy distribution or spectrum as it is known in the field.

Table controlled dynamic bit allocation in a variable rate sub-band

The subject suppressor is an improved form of echo suppressor used in conjunction with adaptive sub-band speech coders. The suppressor analyzes and uses N contiguous sub-bands of a sub-band speech coder. The intermediate results calculated during the normal operation of such speech coders may be analyzed in the suppressor to determine predictions for the echo levels of each sub-band and to set break in and break out thresholds. A substantial performance improvement with little increase in complexity over current echo suppressors is achieved. The subject suppressor may also be used with adaptive transform speech coders in which the corner frequency points define the edges of 'sub-bands' for purposes of this invention. Sub-bands are defined here as contiguous segments of the frequency-energy spectrum. The sub-bands so defined can be formed or analytically divided by a bank of filters as in normal sub-band coders or they can be identified or analyzed as noted above by the corner points of an adaptive transform coder.

Adaptive sub-band echo suppressor

A solid state switching network includes three FET switches or devices arranged in a substantially 'T' (or inverted 'T') configuration. The network is controlled so that in an 'OFF' or non-conducting state two of the FET switches are 'OFF' and one is on. The high 'OFF' impedance of the two FETs work against the low 'ON' impedance of the third FET to provide an open circuit between the input and output of the switching network. The open circuit has greater isolation than is feasible with conventional circuits. The switching network or module is used in several configurations to couple data terminal equipment (DTE) to a communications highway.

FET switch for high frequency signals

This invention utilizes a sectored servo control having dual servo tracks recorded in the servo sector. In addition, the servo sector track portions have been recorded with two 180.degree. flux reversals in each track's polarity. The tracks are generally recorded with DC recording current to set a uniform magnetic polarity. The current is switched twice, i.e., from positive and negative and back again or vice versa for each servo track within the servo sector interval. This permits separation of the sensor, amplifier and servo signal offset voltages from the main servo signal itself. Two samples of the servo control voltage are taken during the servo sector interval and the polarity reversal of the servo track is necessary to allow separation of the offset voltages from a variety of sources from the off track or servo error signal.

Twin track vertical magnetic recording servo control method and

A speech activity detection circuit and method are described in which a digitized sample of the analog speech signal in a communications system is taken n times in a period of time t. The magnitude M of each sample is calculated and the largest value of M which is encountered over a given period t is stored as a peak magnitude M(t). This value is compared to a value M(t-1) which is the smallest value of M(t) from prior periods. The lesser of the two values is stored as the new value for M(t-1). The process is continued for i periods and at the end of the i.sup.th period, the value M(t-1) is multipled by a constant k and the product is stored as the threshold value for the next i periods of time t.

Speech detector with variable threshold

A digital delta modulation compander circuit makes advantageous use of the mathematical truncation created during the computation of step sizes to create a non-linear step size variation which differs from the optimum desired step size but causes convergence recovery during error conditions. It has been discovered that the truncation involved in the inaccurate approximation of mathematical calculation of the step sizes produces an advantageous result which leads to an optimized digital delta modulation compander that will recover from transmission errors over a wider range and with greater efficiency than other methods.

Optimized digital delta modulation compander having truncation effect

A noise reduction circuit and method are described for implementation in a delta modulation system for signal transmission. Under certain conditions when the delta modulator has selected the minimum step size for encoding and transmission, the present technique and apparatus are effective to change the minimum step size in a way which prevents low level noise generation from occurring in the delta modulation system. The technique and circuit can be utilized with most commonly available delta modulators which have means for changing the step size (i.e., the delta) but is used to the best effect on more stable implementations of delta modulators where an integrator is replaced by a digital accumulator and a digital-to-analog converter.

Noise reduction method and apparatus for companded delta modulators

A digital-to-analog converter method and apparatus is disclosed which utilizes a hybrid technique of combined pulse width and pulse rate modulation to achieve improved performance with reduced logic and circuitry requirements. Lower order bits of an N-bit digital data input for conversion to a corresponding analog output voltage level are treated in a manner similar to pulse rate modulation approaches utilized previously. High order bits are handled together in a variant form of pulse width (duration) modulation in which the pulse width required to generate the given analog voltage level corresponding to the high order digital bit inputs is divided into a fixed number of slices in a given sample time, each slice having a width or duration of pulse output which is variable in itself in correspondence to a function of both the high and low order bit value inputs. A low pass filter or integrator combines all of the pulses in a given sample to produce the analog voltage level output.

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Raleigh, NC, United States of America

William G Crouse