Cypress Semiconductor Corporation

Other

William G Baker

Jeffery Scott Hunt

George M Ansel

Sanjay K Sancheti

James E Kelly

Andrew L Hawkins

David Robert Lindley

Jeffrey W Gossett

Kailash Nagarakanti

A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. At least one of the plurality of signals may comprise an identical signal path while in the first mode and the second mode.

Majority vote circuit for test mode clock multiplication

A circuit and method for providing a fast transitioning output buffer that may be configured to operate using either a 3 volt or 5 volt supply voltage. The pullup behaves similarly to a MOS diode, but the circuit lowers the gate voltage on a pullup while the output is being pulled up. The circuit does not affect the final pullup voltage. As a result, a single PMOS device may be used as a pullup device that does not generally require an increased size to support a high operating voltage.

MOS output driver, and circuit and method of controlling same

The present invention is an efficient system and method for flexible masking of output bits from a counter. The maskable counter system and method of the present invention modify the chain carry fed into a counter so that any bit (or bits) of the counter may be masked. A masked bit of a maskable counter system and method is utilized to facilitate user programmable control of multiple configurations in a memory. A maskable counter system comprises a mask register (e.g., a D flip flop), a counter (e.g., a D flip flop), and a masking coordination circuit. The masking coordination circuit permits a carry in signal, a carry out signal, and a counter output bit signal to operate in a normal incrementation manner if a mask bit is not asserted and prevents the counter output bit signal from changing if the mask bit is asserted.

Counter logic for multiple memory configuration

A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. A delay of the output clock signal may be identical when operating in either the first mode or the second mode.

Test mode clock multiplication

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output signal in response to one or more first input signals. The second circuit may be configured to generate a second output signal in response to one or more second input signals. The first and second output signals may be presented to a bond pad.

Electrical ID method for output driver

A method of generating write control signals insensitive to glitches on a data input signal comprising the steps of (A) enabling a write of a first or second value in response to a data input transition, (B) holding in a ready state until the data input is stable and (C) writing stable data into a memory array.

Method and circuitry for writing data

An apparatus comprising a first circuit, a reset circuit and an output circuit. The first circuit may be configured to generate one or more state signals in response to (i) a first and a second write control signals and (ii) one or more control signals. The reset circuit may be configured to generate the one or more control signals in response to (i) a global write signal and (ii) the first and second state signals. The output circuit may be configured to generate a third and fourth write control signal in response to (i) the global write signal (ii) a data input signal and (iii) the first and second state signals. In one example, the third and fourth write control signals may generate a pulse on either the third or the fourth write control signals in response to a transition of the data input signal.

The present invention concerns a method and apparatus for disabling columns using a local fuse decoding system. The present invention uses local decoding in order to use a number of fuses that is less than the number of columns in order to disable column failures. This is particularly useful when the fuse pitch is greater than the column pitch which does not allow for a fuse to be implemented in each column.

Decoder circuit and method for disabling a number of columns or rows in

The present invention concerns a delay circuit that provides a fixed amount of delay that is generally independent of process variations. An input resistance is provided that may be presented to a threshold device, such as an inverter, that may then be presented as an output. The output of the threshold device may also be presented through a feedback path comprising a capacitive device to the input of the threshold device. The feedback through the capacitive load actively resists the movement of the load. As a result, the delay provided by the circuit is generally resistant to process variations.

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Starkville, MS, United States of America

William G Baker