International Business Machines Corporation

Other

William Frederick Shutler

Erich Klink

Hilton T Toy

Eric D Perfecto

Lewis Sigmund Goldmann

Raed A Sherif

Glenn Graham Daves

Roland Frech

Herbert I Stoller

Jason Lee Frankel

John F Vetrero

Anthony Wayne Sigler

Cathy Ann Zadany

Michael J Ellsworth, Jr

William F Beausoleil

Edmund D Blackshear

Hubert Harrer

Joseph M Mosley

Frederick J Aichelmann, Jr

Thomas-Michael Winkel

Ulrich Weiss

Mohanlal Savji Mansuria

Norton J Tomassetti

Vincent F Sollitto, Jr

Richard D Musa

Vito J Tuozzolo

Simone Rehm

Gisbert Gerhard Thomke

Bernd Garden

A jogging structure for translating wiring connections from points in a first grid to corresponding points in a second grid in a chip carrier module is disclosed. In an exemplary embodiment, the structure includes a first translation layer, coupled to the first grid, the first translation layer translating the first grid in an x-axis direction. A second translation layer is coupled to the first translation layer, the second translation layer for translating said wiring connections from the first grid in a y-axis direction, the y-axis direction being orthogonal to the x-axis direction. The second translation layer is further coupled to the second grid.

Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules

A three-dimensional memory module in a repetitively used pedestal connector provides signal paths unique and common to the module at its level and signal paths from the level below unique to and common to modules at levels above. In order to provide a unique signal path from a substrate to each memory module, while using identical pedestal connectors at each level, signal lines are skewed from where they enter the bottom surface of the pedestal connector to where they exit the top surface. For example, each input in a line of inputs is connected to a matching line of outputs, but with a shift of one position between input and output.

High bandwidth 3D memory packaging technique

A sealed electronic circuit module includes a ceramic chip carrier with a top surface, a cover having a mating surface and a seal at the periphery of the carrier between the carrier and the cover. The seal includes a non-metallic soft lower frame, preferably polyimide, atop the carrier at the periphery of the carrier. There is an upper adhesion layer shaped as a matching an upper frame facing downwardly from the cover towards the lower frame. Above the soft lower frame is a lower metal adhesion layer. Between the upper frame and the lower adhesion layer is a solder layer which has been heated to seal the cover to the chip carrier. The soft frame can include a channel through which a metal to metal via-seal is formed by the lower metal adhesion layer and the solder through the channel through the soft layer or there can be a lateral extension of the lower metal adhesion layer to a distal location beyond the periphery of the soft lower frame.

Package with low stress hermetic seal

Disclosed is a multilayer electronics packaging structure, especially for use in a multi chip module. By forming an overlap of signal conductors by the respective mesh conductors, an improved shielding effect is achieved and coupling between signal conductors is reduced. By increasing the via punch pitch such that multiple wiring channels are formed between adjacent vias, wirability is improved and the number of signal distribution layers may be reduced. The new structure thus shows improved electrical properties over the state-of-the-art structures, combined with a cost reduction of about 35%.

MCM&mdash;MLC technology

Low stress hermetic seal

Described is a novel implementation of a medium and high frequency on-module (off-chip)/on-chip power noise filter for power noise sensitive circuits. To achieve this, a second order low-pass approach is used. The first stage capacitor is located on-module (off-chip), and the second stage capacitor is implemented on-chip.

Two-stage power noise filter with on and off chip capacitors

Multilayer module with thinfilm redistribution area

A thermoelectrically cooled integrated circuit package including an insulative module which defines a cavity, a thermoelectric cooler within the cavity, and an integrated circuit chip connected to the thermoelectric cooler, thus providing an integrated circuit package in which the integrated circuit package itself dissipates thermal energy generated by the integrated circuit chip.

Integrated thermoelectric cooling

A dual ported buffer memory for a hierarchical memory, cmprising an addressable memory array for multi-bit words and a multi-bit register. Data is transferred a word at a time between the memory array and a multi-bit bus to a higher level in the memory system and between the memory array and the register. Data is transferred a bit at a time between the register and a single serial line. Concurrent operations are possible for transfers between the memory array and the parallel bus and between the register and the serial line.

Intermediate memory array with a parallel port and a buffered serial port

Growing community of inventors

Wappingers Falls, NY, United States of America

William Frederick Shutler